Alphawave Semi at the Chiplet Summit

The first annual Chiplet Summit was held last week in San Jose and I must say it exceeded my expectations, but I have some advice for the participating speakers and sponsoring companies. A good portion of the content was on WHY chiplets and not HOW. I think we have progressed passed this point and if we keep dwelling on it we will delay the HOW which is critical in moving a new technology forward.

Otherwise I was very impressed and will attend again next year, absolutely.

In regards to content, I would like to call out a company that I admire Alphawave Semi. Not only were they a gold sponsor, Alphawave presented some of the best content and not only can they explain HOW chiplets work they can actually implement chiplets for you in form of a completed ASIC.

Even though the event has passed you can speak directly to the Alphawave people on the topics they covered. We will be writing more about it as well once we go through the materials they have provided.

Alphawave Semi will be a Gold Sponsor at the inaugural Chiplet Summit 2023 located in San Jose, CA on January 24-26, 2023! Catch us at our booth to learn more about our industry leading D2D (Die-to-Die) IP along with our custom silicon expertise integrated into a foundation for prebuilt connectivity chiplets delivering connectivity at a higher bandwidth and lower power than traditional infrastructure solutions.

Chiplet experts from Alphawave Semi will also be participating at Chiplet Summit on panels covering high-speed on-chip interfaces to achieve high performance while avoiding high latency; considerations on cost, chip area, throughput, and support are key in making an interface flexible, comprehensive, and easy to integrate for chiplet interoperability; and how to create a business-friendly structure on chiplet development for a viable marketplace.

Alphawave Semi is a contributing member of the Universal Chiplet Interface Express (UCIe) group and will be discussing the benefits UCIe brings to the ecosystem and market in panel discussions.

Alphawave Semi’s AresCORE16 D2D Connectivity IP is a market leading extremely low-power, low-latency interface IP designed by Alphawave Semi for very high bandwidth connections between two dies that are on the same package and is just one of the ways Alphawave is accelerating the critical data infrastructure at the heart of our digital world.

Panel Chiplet Interfaces

Letizia Giuliano
Tuesday, January 24th | 08:30-Noon

High-speed on-chip interfaces are the key to making the chiplet idea work. High data rates are essential to achieve high performance and avoid high latency. The interfaces also must consume little chip area to avoid reducing the total level of integration, and they must add little to power or thermal budgets. Example buses such as Bunch-of-Wires (BoW) and Universal Chiplet Interface Express (UCIe) are already available. Designers must consider cost, chip area, throughput, and support when deciding which one to use for their specific applications. The interface must be flexible, comprehensive, and easy to integrate with a wide variety of chiplets.

Best Packaging for Chiplets Today

Daniel Lambalot
Thursday, January 26th | 9:00 – 10:00 AM

Packaging is one of the most difficult areas for chiplet designers. Packages must be capable of handling power and heat dissipation, be reasonably priced and small, and be rugged enough for standard applications. Issues of concern include who selects the package and how, which packages are best-suited to chiplet-based designs, what breakthroughs we can expect in packaging over the next few years, and what are the best tradeoffs among size, performance, features, and cost for the many types of packages available today.

Tutorial Chiplet Interfaces

Letizia Giuliano
Thursday, January 26th | 9:00-10:00 AM

The interface connecting chiplets is critical to chiplet-based design. It must be extremely fast, highly reliable, and very flexible. It must also be low-power and take little chip area. There are two major contenders: Universal Chiplet Interface Express (UCIe) from the UCIe Consortium and Bunch-of-Wires (BoW) from the Open Compute Project Foundation. Designers must determine which fits best in their applications, and which is most likely to develop a large support ecosystem

How To Make Chiplets A Viable Market

Clint Walker
Thursday, January 26th | 2:00-3:30 PM

Many articles have discussed how chiplet-based design could become a drop-in business in which designers select the chiplets they want from a marketplace. Obviously, such a concept depends on a viable market in which chiplet designers could make a reasonable return on their investment. Clearly there would have to be standards for chiplets so chip designers would know what they’re getting and how it would integrate into their devices. The chiplet would need to have a specification sheet lists its connections and its characteristics in a specific manner. The chiplet would also have to pass both security and interoperability tests. Clearly such a marketplace will take time to develop and will require an organization to oversee it.

About Alphawave Semi

Alphawave Semi is a global leader in high-speed connectivity for the world’s technology infrastructure. Faced with the exponential growth of data, Alphawave Semi’s technology services a critical need: enabling data to travel faster, more reliably and with higher performance at lower power. We are a vertically integrated semiconductor company, and our IP, custom silicon, and connectivity products are deployed by global tier-one customers in data centers, compute, networking, AI, 5G, autonomous vehicles, and storage. Founded in 2017 by an expert technical team with a proven track record in licensing semiconductor IP, our mission is to accelerate the critical data infrastructure at the heart of our digital world. To find out more about Alphawave Semi, visit: awavesemi.com

Also Read:

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Die-to-Die IP enabling the path to the future of Chiplets Ecosystem