Die-to-Die IP enabling the path to the future of Chiplets Ecosystem

The topic of chiplets is getting a lot of attention these days. The chiplet movement has picked up more momentum since Moore’s law started slowing down as process technology approached 5nm. With the development cost of a monolithic SoC crossing the $500M and wafer yields of large die-based chips dropping steeply, the decision to pursue chiplets methodology is a no brainer. No wonder, companies such as AMD, Intel, Marvel and others who build leading-edge node, large die-size based chips were the early ones to successfully implement chiplets based products. While a chiplets implementation has its own challenges, these companies did not have to deal with the additional challenges of heterogeneous chiplets implementation.

For a broad-based adoption of heterogeneous chiplets implementations, there are several challenges to overcome within an open ecosystem. Packaging is one area but that has already seen lot of advances over the years with innovations including flip-chip, silicon interposer, 2.5D, 3D, chip scale packaging and wafer level packaging. Over the last few years, the area that is receiving lot of attention and investments is chiplets interfaces. Standards for communicating between chiplets are being promoted to standardize interfacing and ease heterogeneous chiplets implementations.

Recently, Intel, AMD, Meta, Arm, Google, Qualcomm, TSMC and ASE formed a consortium to promote an open standard called Universal Chiplet Interconnect Express (UCIe). UCIe 1.0 covers die-to-die physical layer, protocols and software stacks leveraging PCI Express (PCIe) and Compute Express Link (CXL) standards. The Open Domain-Specific Architecture (ODSA) Sub-Project is also working on standardization initiatives.

Letizia Giuliano, Vice President, Solution Engineering at Alphawave IP gave a talk at IP-SoC Silicon Valley 2022 last month. Her presentation focused on design challenges with chiplet integration and open ecosystem solutions. She compared the Die-to-Die (D2D) Interface Figure of Merit for various interface/package combinations and the open ecosystem that is driving chiplets adoption. She closed by presenting Alphawave IP’s configurable D2D PHY interface as a way to navigate the evolving landscape for interfaces for integrating chiplets. You can download her presentation slides from here. The following is a synthesis of the salient points from her presentation.

Design Challenges with Chiplet Integration

With a chiplet integration, a number of nanometer pitch wires that were on-chip turn into package-level interconnects. This introduces signal integrity issues, longer latencies, increased power and test complexities. While advanced package technologies have enabled physical integration of various chiplets with package channels contributing only a few dB of loss, there are other issues to tackle. The tradeoffs are additional space/area, required design effort, complexity and power.

Designing The Optimal System

Traditional connectivity IP consume a lot of power and area. An efficient D2D interface IP is needed to arrive at the right tradeoff between throughput, linear dimension per chip edge and power. The following chart compares the different tradeoff parameters when implementing various interface standards using advanced and standard package technologies.

What is needed is a solution that will optimally suit the type of chiplet/functionality being interfaced. An IP that is configurable to support the various open standards.

Alphawave IP’s AresCORE16 D2D Connectivity IP

Alphawave IP has designed an extremely low power, low-latency interface IP to support very high bandwidth connections between two dies that are on the same package.

The IP implements a wide-parallel and clock forwarded PHY interface for multichannel interconnections up to 16Gbps. The PHY IP is configurable to support the leading standards such as Bunch of Wire (BOW), Open High Bandwidth Interface (OHBI) and Universal Chiplet Interconnect Express (UCIe). The IP is also configurable to support advanced packaging such as Chip-on-Wafer-on-Substrate (CoWoS), Integrated-Fan-Out (InFO) for maximum density, and Organic Substrates for cost-effective solutions for different market segments.

The AresCORE16 D2D connectivity IP’s target applications include high-performance computing (HPC), data centers, artificial intelligence (AI) and networking.

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