TSMC Technology Symposium Review Part II

TSMC Technology Symposium Review Part II
by Tom Dillinger on 04-30-2019 at 10:00 am

TSMC recently held their annual Technology Symposium in Santa Clara. Part 1 of this article focused on the semiconductor process highlights. This part reviews the advanced packaging technologies presented at the symposium.

TSMC has clearly made a transition from a “pure” wafer-level foundry to a supplier of complex integrated… Read More


Design for Fanout Packaging

Design for Fanout Packaging
by Bernard Murphy on 12-12-2016 at 12:00 pm

In constant pursuit of improved performance, power and cost, chip and system designers always want to Image Removedintegrate more functions together because this minimizes inter-device loads (affecting performance and power) and bill of materials on the board (affecting cost). However it generally isn’t possible… Read More


TSMC 10nm Readiness and 3DIC

TSMC 10nm Readiness and 3DIC
by Paul McLellan on 05-03-2015 at 1:00 am

Image RemovedAt the TSMC Technology Symposium last month Suk Lee presented a lot of information on design enablement. Suk is an interesting guy with a unique background in ASIC, Semiconductor, EDA, and now Foundry. In baseball terms that would be like playing infield, outfield, home plate, and umpire!

Around the turn of the millennium… Read More