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Using EM/IR Analysis for Efinix FPGAs

Using EM/IR Analysis for Efinix FPGAs
by Daniel Payne on 05-30-2022 at 10:00 am

I’ve been following the EM/IR (Electro-Migration, IR is current and resistance) analysis market for many years now, and recently attended a presentation from Steven Chin, Sr. Director IC Engineering of Efinix, at the User2User event organized by Siemens EDA. The Tuesday presentation was in the morning at the Marriott Hotel in Santa Clara, and was in the track for the mPower and Calibre PERC tools.

Steven Chin min
Steven Chin, Efinix

Efinix

Steven started with an overview of Efinix, how they were founded in 2012, and their product is a low power and efficient FPGA, which is easier to use. Efinix is endorsed and invested by: AMD/Xilinx, Samsung, Alibaba, HKX, Henderson, AIM, and MAVCAP. Their FPGA technology is built with an array of something called an eXchangeable Logic & Routing Cell (XLR), which is used either as a logic or routing matrix. This approach was chosen to remove the traditional congestion challenge of other FPGA architectures, producing a low power, and a 4X better Power-Peformance-Area (PPA), while reaching 100% utilization ratio.

XLR min
XLR cell

The XLR cell can be fabricated in any foundry process, which helps lower the costs. The first product series was Trion FPGAs, and the second generation of their technology is named Titanium FGPAs.

Design Challenges

The Titanium FGPAs use a 16nm process, and contain from 35K to 1 million Logic Elements (LE), and the design goal was to achieve the highest performance at the lowest power, while minimizing IC layout area. IP had to be integrated from many vendors, and there were multiple power domains  for core cells, analog, memory and IO.

Running EM/IR analysis was key to ensuring adequate power distribution, avoiding hotspots and increasing the silicon yields.

EM/IR Analysis Approaches

The first EM/IR vendor tool used before mPower couldn’t handle the capacity, even when using hierarchical mode. It didn’t handle multiple power domains well, and required a DSPF netlist, which limited analysis to small-sized layouts. Having to use LEF files was a pain, and on top of all that, the CPU run times were quite slow. Looking at the results to find what needed fixing in the IC layout was also tedious.

Using mPower was a big improvement for the engineering team, because they could run the entire chip analysis flat, no abstractions required, making for accurate results. mPower works with a standard Calibre flow, so no need for DSPF and LEF files at all. The power grid was analyzed using RC parasitics based on the xACT tech file. It was easy to toggle between layout and results viewing, making the debug of metal levels for IR drop a quick process.

Here’s the mPower flow used by Efinix:

mPower flow min
mPower tool flow

mPower Usage

Starting inputs for Calibre are the schematic and layout files, and running LVS creates an SVDB file, then used as an input to mPower. Estimated power is another input, and mPower is run flat, reports are read, the failing areas are fixed, and then the tool is run until no errors are reported. Engineers liked using mPower for EM/IR analysis, because it has RVE integration, results are easy to browse, results are fast allowing iterations to complete within a day. Here’s what the GUI looks like:

mPower GUI min
mPower GUI

Run times for mPower on a full-chip Titanium FPGA was just 22 hr, 25min, while using 1.22TB of RAM. Results from a full-chip run showed hotspot tracing and that a IO power cell needed fixing with a 50mV drop. IC layout progressed, and within a week some core block issues were found and the drop was down to 37mV. After fixing the core block issues, the IR drop was reported at 13mV. While tracing the IR drop reports the team found a PLL issue with M4 not strapped properly, so they fixed that within a day.

Efinix found that they could run mPower on full-chip static IR drop analysis within a day, and that the tool found violations that were missed from manual power grid checks. RAM usage and run times have improved since using mPower in early 2021. The improved reliability of their FPGA family of devices means that fewer customer returns happen, and that helps business.

Looking Ahead

Expect ever larger devices, more IP blocks, and migration to smaller process nodes from Efinix. These bigger FPGAs will demand CPU and capacity progress for mPower. Tool users want more flexible methods to mix sources: average, PWL, DC and FSDB currents at the transistor, cell and block levels. The GUI should support the added methods. Finally, 3DIC analysis is desired.

Summary

The team at Efinix evaluated mPower in early 2021, and taped out their first product in the middle of 2021, while a second product taped out in the end of 2021. Using mPower has saved the Efinix team at least a week on every ECO iteration near tape out, because the previous flow required so much manual prep work. Having fast run times, accuracy, and memory efficiency with mPower for EM/IR analysis helped them meet project deadlines.

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