If you hang around engineers for any time at all, the word optimization is bound to come up. The very definition of engineer is to contrive or devise a solution. With that anointing, most engineers are beholden to the idea that their job is creating, synthesizing, and perfecting a solution specifically for the needs of a unique situation.
Several factors have combined to change that thinking in SoC design. Reusing IP in large designs is becoming more than just an option, but now a requirement if the expectation is to release a product in a competitive amount of time. For many functional IP blocks, the choice is fairly obvious: an ARM or MIPS core, a high performance memory subsystem including details of cache coherence, and pieces like a GPU core, a DSP core, or USB interface.
The question becomes how to blend third-party IP, plus any unique new functions, into a design. AMBA has been a vast help, but it provides interconnect – not connectivity. Harnessing a range of diverse IP, coming to timing closure, enabling simultaneous connections between multiple blocks, providing quality of service and prioritization while relieving bottlenecks, simplifying software, and providing other services requires a higher-level approach.
There is also the future to consider. If a design is successful, there is a good chance one will be asked to do it again, and again, and again, with performance improvements, additions, and tweaks for evolving interface requirements. Agonizing over a highly optimized design may quickly unravel when the next iteration is needed, triggering a lengthy redesign and verification process.
Charles Krueger defined four dimensions to IP reuse: abstraction, specialization, integration, and selection. Minutia must be left to trust, with important information abstracted to a higher level. IP needs to be parameterized instead of hardwired. A framework allows IP to be collected into an integrated system, and a strategy for selection helps IP to be found and compared.
Network-on-chip is the manifestation of these principles, becoming the overall framework for integration. It provides abstraction, moving up from the mechanics of AMBA into a higher level using named addressing. It avoids hardwiring and can withstand plugging in a new IP block without having to constantly retool the rest of the design as changes are made. In the case of Arteris FlexNoC, the implementation is configurable, allowing for compatibility with EDA tools and design strategies already in use.
Yesterday’s news that Marvell has adopted Arteris FlexNoC is another indicator that the field is starting to shift. Pumping out more products targeting more application spaces with varying features is the name of the game right now. Until we transition from the wild, wild west scenario that is the IoT – with a lot of unknown territory, few laws, and a gold rush mentality drawing in participants far and wide – flexibility enabled by reuse is far more valuable than optimization.
Reuse is not the antithesis of optimization; it is just a different way of viewing the problem. Instead of measuring success solely in terms of how many transistors are laid down correctly, designers should now be looking at the bigger picture. Optimal design now means being able to abstract the details, scale when needed, pivot when necessary, and adapt to change quickly. Reusing IP in a network-on-chip framework is becoming more and more common.