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There is no technical reason I can think of why you couldn’t make a 7”nm” GAA node. You could also make a 1 micron finFET too, but the effort (both in r/d and in added process complexity) in either case simply isn’t worth it unless your devices are so small that the subthreshold leakage or sram reliability requires the new structure.
There are also alot of practical issue SMIC would run into trying to make a 7”nm” GAA. Samsung talked about direct nanosheet patterning being a key GAA innovation for 3GAE. Given the pitch walking effect when doing SAQP it seems like multiple device widths would be hard without direct printing the features. I feel like developing a GAA process without the latest in etch/dep tooling could be even more challenging than a lack of EUV.
We had this discussion at SEMICON West. The answer was yes (where there is a will there is a way) but cost is a problem and designing a complex SoC to it is another. So the answer really is, no, it is not practical.
As Scotten mentioned, there is still room for SMIC 7nm FinFET optimization but nothing that will get it near TSMC N3 much less Intel 18A.
Here is another questions, does the China consumer electronics (closed) market really need a super charged SoC? My iPhone 14 SoC is severely under utilized and yes I will buy a 15 because I am a fanboy.
Here is another questions, does the China consumer electronics (closed) market really need a super charged SoC? My iPhone 14 SoC is severely under utilized and yes I will buy a 15 because I am a fanboy.
I wish the SE used a cutdown SOC rather than a old chassis for this very reason. But I get why, designing a second weaker SOC is expensive/hard/increases the software burden alot when you support the chips for as long as Apple does.
I wish the SE used a cutdown SOC rather than a old chassis for this very reason. But I get why, designing a second weaker SOC is expensive/hard/increases the software burden alot when you support the chips for as long as Apple does.
It looks like Apple will split the iPhone 15 between TSMC N4 and N3. Clever since the price difference in the phones is significant. Us fanboys will pay more for the N3 without a doubt.
There is no technical reason I can think of why you couldn’t make a 7”nm” GAA node. You could also make a 1 micron finFET too, but the effort (both in r/d and in added process complexity) in either case simply isn’t worth it unless your devices are so small that the subthreshold leakage or sram reliability requires the new structure.
There are also alot of practical issue SMIC would run into trying to make a 7”nm” GAA. Samsung talked about direct nanosheet patterning being a key GAA innovation for 3GAE. Given the pitch walking effect when doing SAQP it seems like multiple device widths would be hard without direct printing the features. I feel like developing a GAA process without the latest in etch/dep tooling could be even more challenging than a lack of EUV.
SAQP probably wouldn't be used for variable-width nanosheets, it could be conventional DUV (@7nm). The nanosheets are not minimal width and are spread out across the cell height.
SAQP probably wouldn't be used for variable-width nanosheets, it could be conventional DUV (@7nm). The nanosheets are not minimal width and are spread out across the cell height.
I don’t think so Fred. Fin pitches at that node were in the low/mid 30s. DUV direct print is at best 80nm. I don’t think 80nm ribbons would easily fit within a 272nm ish HD cell without having very tight gate to gate spacing. Although admittedly I don’t really have any data to back that up given the theoretical nature of this node and my limited industry experience. Even larger HP ribbons should further blow out cell heights. Finally if 80nm was your minimum sheet pitch, I’d have to assume uHD SRAM density would go way down since uHD sram uses 1 fin devices
Edit:
I don’t really know much of anything about cell architecture. But presumably you need at least 5 fin pitches in a cell (2 for devices at least one for n-p spacing and one above and below devices to separate cells). This would give a minimum cell height of 400nm (the same size as 7nm HP/UHP cells).
I don’t think so Fred. Fin pitches at that node were in the low/mid 30s. DUV direct print is at best 80nm. I don’t think 80nm ribbons would easily fit within a 272nm ish HD cell without having very tight gate to gate spacing. Although admittedly I don’t really have any data to back that up given the theoretical nature of this node and my limited industry experience. Even larger HP ribbons should further blow out cell heights. Finally if 80nm was your minimum sheet pitch, I’d have to assume uHD SRAM density would go way down since uHD sram uses 1 fin devices
Edit:
I don’t really know much of anything about cell architecture. But presumably you need at least 5 fin pitches in a cell (2 for devices at least one for n-p spacing and one above and below devices to separate cells). This would give a minimum cell height of 400nm (the same size as 7nm HP/UHP cells).
My understanding was while fins required SAQP (already standardized), nanosheet line pitches were not the same, could cover two fins. So I would imagine a 40-60 nm nanosheet width. In other words, the variable width strategy replaces the fins approach.
In the worst case, if the 80 nm nanosheet pitch were not enough, LELE would be used. But for a 7nm target, like you, I saw a large cell height.
My understanding was while fins required SAQP (already standardized), nanosheet line pitches were not the same, could cover two fins. So I would imagine a 40-60 nm nanosheet width. In other words, the variable width strategy replaces the fins approach.
I hadn’t considered LELE. Based on my limited understanding, that might work; but we are so far beyond my expertise to tell you if there are any issues with that.
semiconductor.samsung.com
