In a recent article on Wikichip they claim that Intel's 10nm process is denser than TSMC's 7nm. (https://fuse.wikichip.org/news/2408...ells-2nd-gen-7nm-and-the-snapdragon-855-dtco/)
However, I think there were 2 different Intel 10nm nodes. The first was used on Cannonlake and yielded very badly. The second updated version is used for Ice lake, but they had to remove COAG (Contact Over Active Gate) and also relax the metal pitch to 40nm in order to get it yield properly. I base this on information that Charlie from Semiaccurate said in a conference call with Susquehanna (www.reddit.com/r/AMD_Stock/comments/bll3pp/notes_from_semiaccurates_cc_with_susquehanna_this)
"COAG (Contact Over Active Gate) was to have saved INTC 10% in area. It completely failed, impacting integrated graphics. This is why the Q4 2017 10 nm Canon Lake had no iGPU."
Those changes would undoubtedly make the second version less dense. I wonder if Wikichip are taking this into account.
What do people here think?
However, I think there were 2 different Intel 10nm nodes. The first was used on Cannonlake and yielded very badly. The second updated version is used for Ice lake, but they had to remove COAG (Contact Over Active Gate) and also relax the metal pitch to 40nm in order to get it yield properly. I base this on information that Charlie from Semiaccurate said in a conference call with Susquehanna (www.reddit.com/r/AMD_Stock/comments/bll3pp/notes_from_semiaccurates_cc_with_susquehanna_this)
"COAG (Contact Over Active Gate) was to have saved INTC 10% in area. It completely failed, impacting integrated graphics. This is why the Q4 2017 10 nm Canon Lake had no iGPU."
Those changes would undoubtedly make the second version less dense. I wonder if Wikichip are taking this into account.
What do people here think?