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Is Intel 10nm really denser than TSMC 7nm?

lefty

Member
In a recent article on Wikichip they claim that Intel's 10nm process is denser than TSMC's 7nm. (https://fuse.wikichip.org/news/2408/tsmc-7nm-hd-and-hp-cells-2nd-gen-7nm-and-the-snapdragon-855-dtco/)
However, I think there were 2 different Intel 10nm nodes. The first was used on Cannonlake and yielded very badly. The second updated version is used for Ice lake, but they had to remove COAG (Contact Over Active Gate) and also relax the metal pitch to 40nm in order to get it yield properly. I base this on information that Charlie from Semiaccurate said in a conference call with Susquehanna (www.reddit.com/r/AMD_Stock/comments/bll3pp/notes_from_semiaccurates_cc_with_susquehanna_this)
"COAG (Contact Over Active Gate) was to have saved INTC 10% in area. It completely failed, impacting integrated graphics. This is why the Q4 2017 10 nm Canon Lake had no iGPU."
Those changes would undoubtedly make the second version less dense. I wonder if Wikichip are taking this into account.
What do people here think?
 
Scott Jones and I will be at SEMICON West next week and will meet with Intel. The goal is to get Intel 10nm on the 7nm TSMC Samsung comparison, at their request. The previous numbers say yes Intel 10nm is denser than Samsung and TSMC 7nm but that may have changed.

The question I have is: Where does Wikichip get their data? I don't see any references. It looks like some of it comes from SemiWiki.
 
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count

Member
I also think the Intel 10nm vs TSMC 7nm comparison is moot now that TSMC is on 7nm+ which is 20% denser than n7. Ryzen 4000 will be on 7nm+, so that will be Intel's direct competition by the time 10nm actually ramps.

I don't think Intel will ever reclaim the process lead now that it has been lost, although I'm sure the spin department will try to claim otherwise.
 

lefty

Member
Scott Jones and I will be at SEMICON West next week and will meet with Intel. The goal is to get Intel 10nm on the 7nm TSMC Samsung comparison, at their request. The previous numbers say yes Intel 10nm is denser than Samsung and TSMC 7nm but that may have changed.

The question I have is: Where does Wikichip get their data? I don't see any references. It looks like some of it comes from SemiWiki.
Yeah, Wikichip don't specify. I assume it's from Intel's white papers
 
I also think the Intel 10nm vs TSMC 7nm comparison is moot now that TSMC is on 7nm+ which is 20% denser than n7. Ryzen 4000 will be on 7nm+, so that will be Intel's direct competition by the time 10nm actually ramps.

I don't think Intel will ever reclaim the process lead now that it has been lost, although I'm sure the spin department will try to claim otherwise.
TSMC 7+ is an orphan due to 6nm. Moving a 7nm design to 7+ is not feasible when it can be moved to 6nm much easier and get better PPA (+18% denisty).

Tom Dillinger wrote it up last month:

 

count

Member
TSMC 7+ is an orphan due to 6nm. Moving a 7nm design to 7+ is not feasible when it can be moved to 6nm much easier and get better PPA (+18% denisty).

Tom Dillinger wrote it up last month:

Wasn't Zen 3 planned to be 7nm+? If so, wouldn't it be the most direct competition to Intel since they will be targeting the same sockets?
 
Wasn't Zen 3 planned to be 7nm+? If so, wouldn't it be the most direct competition to Intel since they will be targeting the same sockets?
Do you have a reference for Zen 3 being 7+? I had not heard that but I did not ask specifically. I was with AMD two weeks ago and we only talked about 7nm.
 

Jozo035

Member
The question I have is: Where does Wikichip get their data? I don't see any references. It looks like some of it comes from SemiWiki.
Problem of David Schor is that he takes Intel's marketing materials as bible and then he adjust rest of the world to match it, even at price of crazy extrapolations...
 

U235

Member
Intel used to get a density boost on their own chips made in their own fabs due to restrictive design rules and (some) full custom layout.

Is a processor all standard cells now, other than cache & memory?
 

mlarson

New member
The question I have is: Where does Wikichip get their data? I don't see any references. It looks like some of it comes from SemiWiki.
It says in article it came from a TSMC/QCOM presentation at the VLSI symposium.

The second updated version is used for Ice lake, but they had to remove COAG (Contact Over Active Gate) and also relax the metal pitch to 40nm in order to get it yield properly.
Utter nonsense.
 
He's right. It actually appears on an official AMD slide: https://hothardware.com/news/amd-zen-3-ryzen-threadripper-epyc-7nm-cpus-transistor-density-uplift
6nm is a recent development. AMD probably already had Zen 3 taped out before it even existed.
Interesting. Do the slides have a date? Was it before 6nm was officially announced (May 2019) ? TSMC 7+ is obsolete now that TSMC 6nm is in play. I'm not sure why AMD would put the effort into 7+ for a small density increase when they can do 5nm or easily migrate 7nm designs to 6nm. I also met with Nvidia and they are still on TSMC 7nm and will migrate to 6nm.

I would really be surprised if AMD and Nvidia do NOT split manufacturing between TSMC and Samsung. Two foundry sources is always better than one and margins are everything for fabless chip companies.

It will be interesting to see what happens at SEMICON West next month. Scott Jones and I will be there and the meeting requests just keep on coming. Intel hired some outsiders for marketing so there are a lot of familiar faces this year.
 
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count

Member
Interesting. Do the slides have a date? Was it before 6nm was officially announced (May 2019) ? TSMC 7+ is obsolete now that TSMC 6nm is in play. I'm not sure why AMD would put the effort into 7+ for a small density increase when they can do 5nm or easily migrate 7nm designs to 6nm. I also met with Nvidia and they are still on TSMC 7nm and will migrate to 6nm.

I would really be surprised if AMD and Nvidia do NOT split manufacturing between TSMC and Samsung. Two foundry sources is always better than one and margins are everything for fabless chip companies.

It will be interesting to see what happens at SEMICON West next month. Scott Jones and I will be there and the meeting requests just keep on coming. Intel hired some outsiders for marketing from so there are a lot of familiar faces this year.
I believe Ryzen 4000 chips taped out on TSMC 7nm+ early this year, and will be in production in 2020 based on what I've seen in AMD slides. I agree that TSMC 6nm looks like a better bet for companies going forward. What node it's on is ultimately moot though, what's important is that Intel is comparing it's next gen chips (limited quantities of 10nm laptop chips aside), to a year old 7nm process and trying to spin that as a victory. The truth is Intel has fallen a full year behind on process technology, and is slipping by the day.
 
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IanD

Member
TSMC 7nm+ and 6nm are both similar PPA, with similar area shrinks from 7nm, both use EUV for some layers. Big difference is that 7nm+ (first EUV process at TSMC) rules aren't compatible with 7nm, so any IP in 7nm has to be re-laid out, which is a big effort so it wasn't popular. After this experience TSMC now came up with 6nm which is backwards compatible with 7nm, new layout/libraries are only needed if you want the area shrink. So 7nm+ is now an orphan process, not many people have used it but those who did may be stuck with it -- it's not clear whether 7nm+ layouts can be used in 6nm. It's clear that 6nm will be the new mainstream process for TSMC customers who don't want the big cost/effort leap to go to 5nm, and it's more dense than Intel 10nm.
 

simoncc2

Member
few reminders from TSMC conference in April 2019 in Santa Clara :
6nm : risk production is planned for 1Q20
N5 : risk production started in March'19 as planned
N5P : performance version of n5 : planned to be ready in 2020

since N5 offer 1.8X logic density reduction compared to N7and N6 only propose 20% compared to N7 for logic density reduction, I believe that 6nm is what we were used to call the FFC node : a cost effective version of a previous node (in our case for 7nm). N5 on the contrary, is available before 6nm and offer more performance, area reduction that N7, so most likely we will see N5 chip in 2020 from AMD. no need to 6nm here.
 
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Portland

Member
We should looking at the manufacturing and what they're doing with ai, ..... etc. Node size is only one factor. I have no doubt and can have denser modes but how many can they make?
 

name99

Member
TSMC 7+ is an orphan due to 6nm. Moving a 7nm design to 7+ is not feasible when it can be moved to 6nm much easier and get better PPA (+18% denisty).

Tom Dillinger wrote it up last month:

Apple A13 will be on 7+, no? That's a pretty big win for an "orphan"!
More generally I think terms like "short-lived node" and "orphan", with their pejorative connotations, are rarely helpful. It's the nature of this space that no process stays leading-edge forever...
More useful is to discuss whether a process did (or did not, or fell short of, or exceeded) its target engineering and business goals.
 

Freebird

New member
I believe Ryzen 4000 chips taped out on TSMC 7nm+ early this year, and will be in production in 2020 based on what I've seen in AMD slides. I agree that TSMC 6nm looks like a better bet for companies going forward. What node it's on is ultimately moot though, what's important is that Intel is comparing it's next gen chips (limited quantities of 10nm laptop chips aside), to a year old 7nm process and trying to spin that as a victory. The truth is Intel has fallen a full year behind on process technology, and is slipping by the day.
I agree I believe Ryzen 4000 will be 7+nm slated for 2H 2020, due to the state of process readiness at TSMC. 5nm will probably be Q4 2021/Q1/2022, maybe earliest production going into Frontier?
The question is when and what products might try to leverage Samsung's EUV processes.
I can see 7nm Navi being migrated to 6nm. Not sure where AMD's custom semi fits in but maybe 7nm+, since Sony 5 product is slated for late 2020? Microsoft also maybe late 2020.
 

Andrei

Banned
The question I have is: Where does Wikichip get their data? I don't see any references. It looks like some of it comes from SemiWiki.
This is quite insulting, but not unexpected from you. Have you considered David sourced it from meetings with Intel engineers and architects such as attending Intel's TechDay briefing events?
 
This is quite insulting, but not unexpected from you. Have you considered David sourced it from meetings with Intel engineers and architects such as attending Intel's TechDay briefing events?
Certainly possible. Generally speaking if you attend an event you reference it. I do see content scraped from Scott Jones without his permission, which happens quite frequently. Scott is the most scraped blogger on SemiWiki. Most websites such as SemiWiki contain copyrighted material (Copyright © 2019 SemiWiki.com. All rights reserved. ) so permission is required. But today's media is like the Wild Wild West so anything goes.

I don't see the insult in my comment, it was merely an observation. It is very hard to believe anything you read on the internet these days so I feel references are important. Just my opinion of course.
 
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