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The Intel 4 process node has Intel’s highest Day-Zero yields in a decade.
www.tomshardware.com
In the process section intel prettied up their VLSI graphs. Besides the eye candy the more interesting thing is that MTL yields are better than at the Skylake or Tigerlake launches on the fixed 14nm and 10nm SF nodes respectively.
The Intel 4 process node has Intel’s highest Day-Zero yields in a decade.
www.tomshardware.com
In the process section intel prettied up their VLSI graphs. Besides the eye candy the more interesting thing is that MTL yields are better than at the Skylake or Tigerlake launches on the fixed 14nm and 10nm SF nodes respectively.
The Intel 4 process node has Intel’s highest Day-Zero yields in a decade.
www.tomshardware.com
In the process section intel prettied up their VLSI graphs. Besides the eye candy the more interesting thing is that MTL yields are better than at the Skylake or Tigerlake launches on the fixed 14nm and 10nm SF nodes respectively.
The Intel 4 process node has Intel’s highest Day-Zero yields in a decade.
www.tomshardware.com
In the process section intel prettied up their VLSI graphs. Besides the eye candy the more interesting thing is that MTL yields are better than at the Skylake or Tigerlake launches on the fixed 14nm and 10nm SF nodes respectively.
For Intel products this a good sign, absolutely. For the foundry business there is a lot of buzz about 18A. I'm still trying to figure out who the whale customer is though. Great event, Intel really rolled out the red carpet for the media. TSMC OIP is next week. We should know what's what after that.
Chiplets really are going to disrupt the foundry business. Just wait and see......
I agree. Especially for chips with very complex logic. Design cycles will be quicker and cheaper, which should accelerate innovation. On the other hand, let's not kid ourselves, chiplet designs may have power and performance challenges compared to single die designs for some applications. But I think, overall, chiplets are a huge win for the industry.
Yeah I don't think you can find anyone who would say the process tech was in a great place for BDW or ICL, nevermind CNL (even if I think it would be funny to see it plotted here). Either way skylake and tigerlake were very clearly fine on the yield front given how intel made a boatload of those medium die sized client parts and large DC parts without having margins fall off a cliff.
Also I just noticed the plot says they are equalized for a 100mm^2 die. No clue why they chose to have it be a hard to see grey (especially when it is good news like that), but here we are.
Yeah I don't think you can find anyone who would say the process tech was in a great place for BDW or ICL, nevermind CNL (even if I think it would be funny to see it plotted here). Either way skylake and tigerlake were very clearly fine on the yield front given how intel made a boatload of those medium die sized client parts and large DC parts without having margins fall off a cliff.
Also I just noticed the plot says they are equalized for a 100mm^2 die. No clue why they chose to have it be a hard to see grey (especially when it is good news like that), but here we are. View attachment 1459
Should the yield of "Intel 4" in Meteor Lake be calculated only based on the CPU tile? Since all the other parts are made by tsmc N5/N6.
I also notice the figure title is Client Yield during "Launch Quarter". Since Dec 14 hasn't come, does that means the yield of Intel 4 is "projected yield"?
Could be yield of the full system in package, but they also had some talk about great yields of the full packaging process too.
I think MTL is late because it is *complex*. Looking at all the newly divulged details, MTL has so many firsts for Intel it's mind bending... 4 tiles, NOC fabric, a 3rd tier of core (E low power island), a SOC chiplet with all media engines in it, a new N5 GPU tile, VPU tile... so yea, overall it's probably microcode/firmware/software/ISV/OEM complexity that slowed MTL. From a manufacturing perspective, it seems to be on point (finally).