Scotten Jones
Moderator
Samsung's first generation 7nm process is double diffusion break, I believe single diffusion break doesn't come in until their third generation.
Intel 7nm on track
- Thread starter KingSeGa
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Samsung's first generation 7nm process is double diffusion break, I believe single diffusion break doesn't come in until their third generation.
Scotten Jones
Moderator
TSMC did publish a paper on a germanium GAA. They have been working on Germanium for a long time.
Scotten Jones
Moderator
Yes, horizontal nanosheets share a lot of steps in common with FinFETs, that is actually one of the reasons so many people think they are the logical successors to FinFETs.
There are however still significant challenges and the new steps are not easy.
To the best of my knowledge no one has made horizontal nanosheets with multiple threshold voltages yet and getting the work function material stacks into the narrow gaps between layers will be very difficult. I don't think a full up integrated process flows has been done yet either.
Samsung aims high and misses frequntly, TSMC aims carefully and rarely misses. I could definitely see TSMC doing a FinFET at 3nm if they thought it could meet their performance goals and was lower risk.
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I think you've hit the nail on the head there. As a component IDM Intel is completely driven by in-house super-high-margin CPU business, so they aim very high (but with big risk) and sometimes miss disastrously (10nm). As a system IDM Samsung is mostly driven by in-house lower-margin AP/DRAM business so can accept some risk (because if it works they win big-time on both process and Samsung products) so they aim high but often miss. TSMC is entirely driven by external customers so they only gain from selling wafers, this means big risk is not acceptable, so they are careful and (at least recently) almost always meet or exceed their targets.
Basically for an IDM the benefits of being first/best are higher because they "move up the value chain" by selling products not components, so they can take bigger risks because the reward of winning is also higher. As a pure-play foundry TSMC have to play it safe because of only selling wafers -- if their yield is low they still have to deliver working chips at agreed prices (if this is the contract), Samsung foundry can swallow this loss because the chaebol makes more back on product sale profits. Intel could do the same in the past for CPUs but it's more difficult now with more competition, and nothing could get over their 10nm process problem.
Nanosheets do look attractive but as Scott says there are many obstacles to using them in a usable mass production process as opposed to an IEDM paper. All the advanced FinFET processes use multiple metal gate stacks with different work functions (up to 4?) for the different transistors; this is difficult enough to do with one FinFET gate because they need separate process steps, so now imaging doing all this 3 times over for a 3-stacked nanosheet transistor...
Scotten I agree that TSMC has made decisions based on minimizing risk and delivering on time to market to their customers. Intel and GF seemed to have great processes on paper but both struggled to deliver a process which worked in HVM. Intel bit off a lot more than they could chew at 10nm - Cobalt for metal, cobalt contacts, SAQP for metal, COAG. The result was that each of these in itself is very complex, but the nett combined effect basically made the process unmanufacturable. The new Intel 10nm which will be in HVM in H2 2019 is likely to have canned COAG and cobalt for metal with also a relaxation of MMP to 40nm to avoid SAQP on metal. GF too seems to have not had much progress with their PDKs before pulling the plug quoting financial reasons.
TSMC's execution on 7nm was solid and based on pragmatism and predictability. TSMC avoided risk to time to market by sticking to SADP for metal and not having cobalt for metal or contacts. At 5nm TSMC is introducing cobalt in a more measured approach for vias and contacts, according to IanD. TSMC 5nm is proceeding very well according to industry observes like yourself and Daniel and also according to TSMC statements where they have stated Q2 2019 for risk production and first tapeouts and Q2 2020 for HVM.
I still think that TSMC is introducing new technologies in a phased and disciplined manner.
N7 - SADP, DUV
N7+ - DUV/EUV
N5 - EUV, cobalt
N5+ -
N3 - GAAFET ?
TSMC is handling the risks of leading edge node development with utmost engineering and management discipline. TSMC has come a long way in the past decade from the canned 32nm process and early troubles with 28nm yield and supply. Their execution from 16nm FF is almost flawless with very sensible tradeoffs to hit time to market and schedule predictability. Kudos to TSMC.
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Scotten Jones
Moderator
"Intel 10nm which will be in HVM in H2 2019 is likely to have canned COAG and cobalt with also a relaxation of MMP to 40nm to avoid SAQP on metal."
Where does this come from, my expectation is the 10nm process going into high volume manufacturing next year will be the exact same process they are running now with improved yield.
TSMC has used DUV since 350nm and SADP since 20nm.
10nm has SAQP
7nm adds cobalt
7+ adds EUV
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Scotten
I am going by charlie's claims. I doubt its the exact same broken 10nm process on which Cannonlake was made.
Intel guts 10nm to get it out the door - SemiAccurate
oh btw i did not mean TSMC 7nm did not have SAQP. I meant SADP for metal. We known SAQP was introduced for fins at TSMC N10. btw can you confirm for sure that TSMC 7nm has cobalt. There is no information to confirm the same even from TSMC's 7nm IEDM 2016 paper.
IEDM 2016 – Setting the Stage for 7/5 nm | Siliconica
Scotten Jones
Moderator
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So Scotten you can confirm that TSMC 7nm uses cobalt for contacts. Is that correct ? Great information. Thanks.
There have been various rumours about what Intel are doing to fix their 10nm yield problem, including going from 36nm to 40nm MMP and ditching SAQP for interconnect, removing cobalt for interconnect, and removing COAG (said to have been the reason they couldn't get any GPU yield on the i3-8121U).
Whatever the exact truth is, there is bound to be some impact on density below the much-vaunted Intel numbers (probably now similar to or maybe even a bit lower than TSMC), and more to the point relayout of all custom IP (which Intel have a *lot* of) as well as new standard cell and RAM libraries which means a big delay -- normally fundamental layout changes to a process like this need re-characterisation of libraries and IP before products can be taped out.
Best guess is that the "new" Intel 10nm process (and products made on it) will be at least a year behind TSMC 7nm even if things go well, which then puts it directly up against TSMC 7nm+ (partial EUV) which will be ~20% denser using the high-density process/libraries, and probably faster (at the same density) than Intel using high-speed process/libraries.
Intel must be hoping that their promises of delivering their 7nm process on-time (whatever that means...) using a different team pay off, but it seems impossible that it will catch up with TSMC 5nm which will be in risk production in 2Q2019.
(by the way, I said that TSMC 5nm had cobalt for vias because this is public knowledge, I didn't say that TSMC 7nm had cobalt (or didn't) because this isn't public...)
Whatever the exact truth is, there is bound to be some impact on density below the much-vaunted Intel numbers (probably now similar to or maybe even a bit lower than TSMC), and more to the point relayout of all custom IP (which Intel have a *lot* of) as well as new standard cell and RAM libraries which means a big delay -- normally fundamental layout changes to a process like this need re-characterisation of libraries and IP before products can be taped out.
Best guess is that the "new" Intel 10nm process (and products made on it) will be at least a year behind TSMC 7nm even if things go well, which then puts it directly up against TSMC 7nm+ (partial EUV) which will be ~20% denser using the high-density process/libraries, and probably faster (at the same density) than Intel using high-speed process/libraries.
Intel must be hoping that their promises of delivering their 7nm process on-time (whatever that means...) using a different team pay off, but it seems impossible that it will catch up with TSMC 5nm which will be in risk production in 2Q2019.
(by the way, I said that TSMC 5nm had cobalt for vias because this is public knowledge, I didn't say that TSMC 7nm had cobalt (or didn't) because this isn't public...)
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Intel recently seems focused on More than Moore approaches like 3D heterogeneous integration, it looks like it is no longer banking on tick-tock. Intel Steps Toward Heterogeneous Integration | EE Times
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Ian
We have not seen any public info about TSMC 5nm having cobalt vias as there has not been any IEDM , ISSCC or VLSI paper presented on the same. I heard it from you the first time here. btw are you allowed to confirm that TSMC 7nm has cobalt contacts now that the process is in HVM and we have million of mobile SoCs built at TSMC 7nm shipping. I am genuinely excited at what cobalt contacts could mean for Zen 2 and Ryzen 3000 series. We have been hearing rumours of 5 Ghz max clocks on Ryzen 3000 from multiple leaks and I am wondering if thats even remotely possible without cobalt contacts.
The transistor density may be reported differently for the same process; like Intel 10nm reported as 100.8 million transistors per sq. mm (Core i3-8121U), TSMC 7nm as 83.9 million transistors per sq. mm (A12). TSMC aims for 1.8x higher density at 5nm.
But Intel usually has the superior transistors correct? Just looking at the optimized 14nm+ vs even 12nm from Globalfoundries CPU from Intel and AMD. Intel still usually wins the benchmarks.
I think past node results cannot be projected now without a lot of risk, generally. Intel had the most aggressive density cadence, so they are likely to hit the issues more visibly than if proceeding with fractional nodes.
I found it interesting that since 2014 TSMC has been building up a strong cut mask IP portfolio.
Samsung's layout style is quite public, and seems to differ from other foundry players. They are trying to keep the more flexible legacy layout style that was common during 90nm, but this is impossible to scale down even with their EUV tools.
Qualcom has already taped out to Samsung 7nm. I am not aware of Nvidia using Samsung 7nm. I do know that all 7nm customers were concerned about capacity and were looking at different options, especially after GF stopped 7nm development and Intel fumbled 10nm.