Intel 7nm on track

[IanD]

Ian
We have not seen any public info about TSMC 5nm having cobalt vias as there has not been any IEDM , ISSCC or VLSI paper presented on the same. I heard it from you the first time here. btw are you allowed to confirm that TSMC 7nm has cobalt contacts now that the process is in HVM and we have million of mobile SoCs built at TSMC 7nm shipping. I am genuinely excited at what cobalt contacts could mean for Zen 2 and Ryzen 3000 series. We have been hearing rumours of 5 Ghz max clocks on Ryzen 3000 from multiple leaks and I am wondering if thats even remotely possible without cobalt contacts.

Before installing a process like 7nm you have to supply TSMC with a list of every individual who will be allowed to see the information, all of which is covered by a tight NDA -- and this remains true no matter how many chips TSMC have shipped. The use of cobalt vias at 5nm seems pretty well known (or speculated on, or blindingly obvious) as the standard approach, which is what I based my comments on.

Using cobalt for vias is not a cure-all magic bullet for speed; what it does do is increase current capacity without electromigration problems, and tightens up the distribution of resistance -- with copper vias the maximum resistance is many times typical, with cobalt the multiple is smaller. Maximum speed for a process nowadays is more a function of decisions about library height/fin count than the raw transistors and materials -- there will be a much bigger performance/power difference between "mobile" and "high performance" cases in a given process than between foundries at a given geometry, because they all use similar equipment and techniques.

If Zen 2 can be pushed as high as 5GHz it's likely to be because AMD chose high-speed low-density libraries (e.g. 9-track 4-fin with DDB) instead of low-speed high-density ones (e.g. 6-track 2-fin with SDB), together with a performance-oriented metal stack (fewer minimum pitch layers, tapered width higher metal, thick top metal with MIM decoupling) instead of a density-oriented one (more fine-pitch metal, thinner higher metal) --- but all these are elements of the same basic 7nm process, the recipe you choose from the huge bag of ingredients is up to you.

Intel would always have used high-performance options, TSMC used to introduce high-density ones first because that was their big customer base, but now they also see HPC/CPU as a priority so are making suitable process options available from the start.

 

[IanD]

The transistor density may be reported differently for the same process; like Intel 10nm reported as 100.8 million transistors per sq. mm (Core i3-8121U), TSMC 7nm as 83.9 million transistors per sq. mm (A12). TSMC aims for 1.8x higher density at 5nm.

And don't forget that the reasons Intel got such high density (SAQP cobalt interconnect, COAG) are the ones that they're dropping (which will lower density) to fix their 10nm yield nightmare -- better to have 84M working transistors per mm2 than 101M non-working ones...

 

[Dayman58]

And don't forget that the reasons Intel got such high density (SAQP cobalt interconnect, COAG) are the ones that they're dropping (which will lower density) to fix their 10nm yield nightmare -- better to have 84M working transistors per mm2 than 101M non-working ones...

Assuming that is what they are doing sure... However Murthy recently stated at NASDAQ 39th Investor Day that Power, Performance and Area specifications are the same from the ones announced in 2014.

The ambitions for 10 haven’t changed. I mean even though we have had the trials and tribulations with 10, the power and performance and transistor density targets that we set in 2014 remain the same.

 

[KingSeGa]

EUV should be better for Intel I'd assume. But I'm starting to think TSMC and Samsung will overtake them eventually and possibly completely.

 

[raghu78]

Before installing a process like 7nm you have to supply TSMC with a list of every individual who will be allowed to see the information, all of which is covered by a tight NDA -- and this remains true no matter how many chips TSMC have shipped. The use of cobalt vias at 5nm seems pretty well known (or speculated on, or blindingly obvious) as the standard approach, which is what I based my comments on.

Using cobalt for vias is not a cure-all magic bullet for speed; what it does do is increase current capacity without electromigration problems, and tightens up the distribution of resistance -- with copper vias the maximum resistance is many times typical, with cobalt the multiple is smaller. Maximum speed for a process nowadays is more a function of decisions about library height/fin count than the raw transistors and materials -- there will be a much bigger performance/power difference between "mobile" and "high performance" cases in a given process than between foundries at a given geometry, because they all use similar equipment and techniques.

If Zen 2 can be pushed as high as 5GHz it's likely to be because AMD chose high-speed low-density libraries (e.g. 9-track 4-fin with DDB) instead of low-speed high-density ones (e.g. 6-track 2-fin with SDB), together with a performance-oriented metal stack (fewer minimum pitch layers, tapered width higher metal, thick top metal with MIM decoupling) instead of a density-oriented one (more fine-pitch metal, thinner higher metal) --- but all these are elements of the same basic 7nm process, the recipe you choose from the huge bag of ingredients is up to you.

Intel would always have used high-performance options, TSMC used to introduce high-density ones first because that was their big customer base, but now they also see HPC/CPU as a priority so are making suitable process options available from the start.

Thanks for the explanation Ian. Yeah the 73 sq mm die size for Zen 2 chiplet with 8 cores,32MB L3 cache and some Infinity Fabric circuitry seems fairly large. AMD is likely to have gone with the highest performance libraries whatever they are. btw TSMC only mentioned the 7.5T cells in their 2018 symposium when comparing performance improvement vs 6T mobile process cells. Last year TSMC mentioned both H360(9T) and H300 (7.5T) cells in their presentations. So it was surprising that there was no mention of 9T in 2018. Anyway things are looking good if we interpret Scotten and your comments as cobalt contacts being present in TSMC 7nm process. We will know soon once techninsights publishes a cross sectional TEM image of TSMC 7nm logic cell.

EUV should be better for Intel I'd assume. But I'm starting to think TSMC and Samsung will overtake them eventually and possibly completely.

TSMC has overtaken Intel already as they are atleast 12-15 months ahead to market with their 7nm process which is roughly equivalent to Intel 10nm process in density. Samsung will probably have 7nm EUV products at roughly the same time as the first Intel 10nm products arriving in late 2019. TSMC is on track for 5nm risk production in Q2 2019 and HVM in Q2 2020. Intel has not provided any timeline for their 7nm and its unlikely to arrive before late 2022 as there are atleast 3 CPU generations planned on their 10nm.

 

[Fred Chen]

And don't forget that the reasons Intel got such high density (SAQP cobalt interconnect, COAG) are the ones that they're dropping (which will lower density) to fix their 10nm yield nightmare -- better to have 84M working transistors per mm2 than 101M non-working ones...

Yes, they've probably strongly considered that (without admitting so) as well as any differences from TSMC.

 

[Fred Chen]

I came across this transistor density benchmark at anandtech, which came out 10 days ago: Spotted: Qualcomm Snapdragon 8cx Wafer on 7nm I think it will still be edited and updated. I am a bit surprised by the Kirin 980, but it seems they went out to verify it: ChipRebel Releases Kirin 980 Die Shot: Cortex A76's & Mali G76 in View

 

[IanD]

Assuming that is what they are doing sure... However Murthy recently stated at NASDAQ 39th Investor Day that Power, Performance and Area specifications are the same from the ones announced in 2014.

Well his pants must be on fire, because it's 100% certain the changes Intel are making to 10nm will reduce density.

 

[IanD]

@raghu78, there are 7nm cell libraries in various flavours from TSMC, ARM, and Synopsys to name just three. These variously include 1-fin to 4-fin, 6T to 9T, different CPP (57nm and 64nm), different gate lengths and transistor types, different VDD -- but not in all combinations because the qualification effort would be immense, so each vendor chooses a few popular options which work well together, some focus more on low-power and others more on high-performance depending on who their customers are.

Usually all varieties can be mixed (some in the same block, some in different blocks) on the same chip, depending on how much benefit they deliver and how much the customer is willing to spend. The only fixed choice which has to be made between density and performance is the metal stack; compact low-power libraries need a lot of routing resources so use more fine-pitch layers, high-performance libraries are less tightly packed and need faster long-distance routing and better power grid so use more thicker layers. But you can still use one type of library with the other metal stack, just with lower density or lower performance.

 

[hist78]

Assuming that is what they are doing sure... However Murthy recently stated at NASDAQ 39th Investor Day that Power, Performance and Area specifications are the same from the ones announced in 2014.

In today's Intel corporate culture, the word "target" is more or less a conceptual idea, not necessary a nonnegotiable commitment. For example their 10nm "target" HVM date has been changed several times so far.

 

[Wilco1]

The transistor density may be reported differently for the same process; like Intel 10nm reported as 100.8 million transistors per sq. mm (Core i3-8121U), TSMC 7nm as 83.9 million transistors per sq. mm (A12). TSMC aims for 1.8x higher density at 5nm.

Be careful when quoting such numbers in the same sentence - the TSMC one is actual achieved density in real products (Kirin 980 does 93.1 million transistors/mm^2). On the other hand Intel's 100.8 number is just marketing (or fake news if you like) and will never be achieved in any shipping product.

According to the link, a quad-core 14nm Skylake achieves just 14.3 million transistors/mm^2. The i3-8121U is a 70 mm^2 dual core - if the 10nm scale factor was really 2.7x you'd expect it to be much smaller, around 45mm^2, and have 4 rather than 2 cores. Even if we accept the 2.7x scale factor, it means the density of any future 10nm Intel CPUs will remain well below 40 million transistors/mm^2.

 

[Fred Chen]

Be careful when quoting such numbers in the same sentence - the TSMC one is actual achieved density in real products (Kirin 980 does 93.1 million transistors/mm^2). On the other hand Intel's 100.8 number is just marketing (or fake news if you like) and will never be achieved in any shipping product.

According to the link, a quad-core 14nm Skylake achieves just 14.3 million transistors/mm^2. The i3-8121U is a 70 mm^2 dual core - if the 10nm scale factor was really 2.7x you'd expect it to be much smaller, around 45mm^2, and have 4 rather than 2 cores. Even if we accept the 2.7x scale factor, it means the density of any future 10nm Intel CPUs will remain well below 40 million transistors/mm^2.

Noted, thanks

 

[KingSeGa]

I guess Intel has admitted defeat! After looking back over the write ups. Intel approach is very aggressive which could delay 7nm further. I definitely believe like many of you have said. TSMC and Samsung will overtake them. It's a matter of time.

https://www.fudzilla.com/news/47828-intel-claims-qualcomm-is-a-monopolist

 

[Portland]

I wouldn't bet on a fab in maricopa county. Build it somewhere where people would feel safe.

 

[mhagmann]

Last week when the announcement was made I read that INTEL will be entering the 7-nm node with SAMSUNG as a partner--And that SAMSUNG will do the fabrication.

1. Please tell me if this is correct--I can send a reference.
2. Please guess what the role of INTEL might be in their partnership.
3. If GlobalFoundries discovered that the economics at 7-nm do not work for them I believe this, but I must ask what causes the difference. For example, would TSMC or SAMSUNG have an advantage due to their location such as government support or less taxation?

 

[Scotten Jones]

Last week when the announcement was made I read that INTEL will be entering the 7-nm node with SAMSUNG as a partner--And that SAMSUNG will do the fabrication.

1. Please tell me if this is correct--I can send a reference.
2. Please guess what the role of INTEL might be in their partnership.
3. If GlobalFoundries discovered that the economics at 7-nm do not work for them I believe this, but I must ask what causes the difference. For example, would TSMC or SAMSUNG have an advantage due to their location such as government support or less taxation?

Not true, IBM is helping Samsung, Intel is gearing up Fab 42 for 7nm.

 

[Portland]

Intel is making a $5 billion investment at their fab in israel. That's all we really know the rest is speculation. Companies like to keep their know-how and equipment secret. My guess that node size isn't the only race going on, how much firepower you have in manufacturing in particular robotics is also important.

I think intel feels comfortable what they have with 10nm.

 

[JohnnyFox]

Intel is making a $5 billion investment at their fab in israel. That's all we really know the rest is speculation. Companies like to keep their know-how and equipment secret. My guess that node size isn't the only race going on, how much firepower you have in manufacturing in particular robotics is also important.

I think intel feels comfortable what they have with 10nm.

Intel did not announce that, the Israeli government announced a grant if Intel decide to invest in building a new fab there. Other Intel sites are also bidding for new fab construction also, I think we will know where that $5 billion is going this year.

 

[Portland]

I'm more interested in the "firepower" needed to make 10nm semis. That's the real question.

I read something on chiportal that 7nm tsmc may not be as far along as thought.

 

[IanD]

I'm more interested in the "firepower" needed to make 10nm semis. That's the real question.

I read something on chiportal that 7nm tsmc may not be as far along as thought.

Since TSMC have already shipped tens of millions of chips to Apple and HiSilicon (and many other customers), it's difficult to see what chiportal might mean...