How is backside power really done?

[Tanj]

The carrier wafer is not removed and the signals as well as power have to come in through the backside. The backside power network is relatively sparse so there is plenty of room to bring in the signals.

The final device wafer is so thin that it wouldn't survive carrier wafer removal.

It will make hybrid bonding pairs more complicated.

 

[milesgehm]

Through silicon vias are formed through the device wafer from the back (this will depend on whose process it is, in some versions they could be created from the front and revealed during wafer thinning). I have discussed the Imec process with Buried Power Rail here: https://semiwiki.com/events/314464-imec-buried-power-rail-and-backside-power-delivery-at-vlsi/

What a great post. Thanks. This is amazing "in some tests they thinned wafers until they hit the shallow trench isolation and they still got good device performance after annealing the wafer."

 

[Scotten Jones]

The connection is from the side just like for the Power Via.

"As a side note why do you think that AMAT and intel have a different definition of what BPR is from IMEC? The engineers from both firms are far from dummies, and they both contribute to IMEC. The difference in opinion and definition strikes me as very odd."

No idea, all I know is that Imec told me the AMAT diagram is wrong with respect to what Imec with BPR does.