Mr Blue, let me get in on this. I like the idea of simulating a CPU (or 2) for 4 clock cycles. To tell you the truth, I was going to do something like this anyway, like add 2 numbers. Let's do Chris's stuff for free. Maybe he can have an easier time with an investor.
Note, I cannot distribute any foundry stuff, so we will use my standard cells. They are a little larger than what the foundry provides. We went with 3 fins.
CPU: The open source WARP-V (preferred 32 bit). I just called Steve Hoover. He is in.
Process: TSMC16 and GF14 (I want to do both)
FinFETS: Standard threshold
L1 cache: Gimme a number of SRAM cells. If not, I will pick.
L2: Let's just stick to L1 + HBM3 to keep it simpler. We can make the interposer on Skywater.
Synthesis: I will use Yosys, unless somebody wants to run Synopsys. I can supply liberty files on our stdcells
P&R: We have it
Analog blocks: We got it, including an NRZ SerDes.
Clock: 6.4GHz or 3.2GHz
Mr. Blue, you are going to love (or hate) this. I called
@simguru (blast from the past) and asked him to show off his cosimulation abilities. I told him that he is not allowed to have an alias like that without being called out on it. Steve Hoover and I will handle the cosimulation in parallel.
No funds change hands and no advertising. This is a SemiWiki freebee.
We won't MPW it, but we will get everything else ready on it, both simulation and layout. No eFPGA (yet)
