GAA Process Video from Applied Materials
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If anyone was wondering what makes me say that I think litho will have a either a stable or slightly smaller share of logic TAM, or that the minimum feature sizes were on the level of individual atoms; this is why. To me it seems like HNS-FETs require more innovation than the development of the first finFETs did. Granted the only planar process I have ever touched was a VERY simple 10 micron planar CMOS in college, so take what I say as you will.
When approaching NSFET or RibbonFET, BS-PDN/PowerVia, and feature size down to tens of atoms, there is always a question: Moore's law reaches the physical limit of dimension patterning? What we see now is ASML promoting their Hi NA EUL scanner to print features with CD ~8nm and pitch ~16nm to mitigate low NA EUVL double/triple patterning challenges in advanced nodes (whatever A10 or 10A). The Hi NA tool price is ~US$400M with expecting 2x WpH (wafer per hour) which is very challenging in process and economically. I would expect there will be low single digit layers adopted Hi NA EUVL in 10A and beyond. On top of this, it will be quite possible litho CapEx would keep stable in the level of weighting 25-30%.
In this video, it looks like intuitively that process seems not that complex and should be ready soon. But in reality, Samsung/tsmc/intel have worked on it with WFE vendors for 5~10 years and eventually "WILL" ramp it by 2025. One challenge in the video is how to measure the underlay CD or detect the remain defect in removing sacrificial SiGe layers. AMAT mentioned their tools of PROVision and PrimeVision (electron beam as probe) to fit the requirement. It could be not that easy and become even challenging when the stacking layers to be increased, like the CFET in the future.
Will the 3D packaging become the savor and create paradigm shift? Let's see.
TSMC: Ecosystem for 2nm Chip Development Is Nearing Completion
I think the bigger issue is one of power performance. Smaller BEOL means worse RC which means any transistor level enhancements become invisible. Also we get ever closer to the physical limit for a switch even acting as a switch, with electron tunneling becoming a bigger issue. GAA and 2D materials will help, but physics are physics the question is just how close can we get to said limit. If a strong 3D roadmap can be established we can just side step the issue of dimensional scaling like NAND did and DRAM is about to do. Either way both issues are a post 2030 problem since the path to 40nm CPP, increased backside functionality, and CFETs look pretty clear.
I have no doubt it will be high yielding in 2025, GAA has been cooking for over a decade. My comment was more so that I think once everything is said and done, that more work/innovation was needed to commercialize this new architecture than it was with planar -> finFET. I suppose I could see what you mean on the flow not really being that many more steps. But as an etch person I can tell you that when you look at individual process steps (as opposed to the whole flow) that almost anything can look easy to do on a powerpoint
. The innovation I see from all of the equipment vendors really is just something else in this materials and architectural enabled era of scaling!I have no clue how the boys and girls in defmet do it, but they deserve a raise.
I doubt it. It is an excellent supplement, but as I have stated before it isn't a tide that will raise all boats like marching down the "Moore's Heuristic" cost curve. If your cost per FET isn't scaling, the only way 3D allows for lower cost per function is by moving components that don't scale off to more economical nodes or better yields from smaller dies. Put another way if the new nodes get more expensive per function than chip costs will rise after you get your one time cost reduction from disaggregation.
ISS 2024 – Logic 2034 – Technology, Economics, and Sustainability - Semiwiki
For the 2024 SEMI International Strategy Symposium I was challenged by members of the organizing committee to look at where logic will be in ten years from a technology, economics, and sustainability perspective. The following is a discussion of my presentation. To understand logic, I believe it...
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