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ASML 2023 Earnings Call Discussion

Daniel Nenni

Admin
Staff member
Today ASML Holding NV (ASML) has published its 2023 fourth quarter and full-year results:
  • Q4 net sales of €7.2 billion, gross margin of 51.4%, net income of €2.0 billion
  • Quarterly net bookings in Q4 of €9.2 billion2 of which €5.6 billion is EUV
  • 2023 net sales of €27.6 billion, gross margin of 51.3%, net income of €7.8 billion
  • ASML expects 2024 net sales to be similar to 2023
  • ASML expects Q1 2024 net sales between €5.0 billion and €5.5 billion and a gross margin between 48% and 49%


Roger Dassen CFO
Thank you, Peter and welcome, everyone. I will first review the fourth quarter and full year 2023 financial accomplishments and then provide guidance on the first quarter of 2024.

Let me start with our fourth quarter accomplishments. Net sales came in at €7.2 billion which is just above our guidance, primarily due to more installed base business. We shipped 10 EUV systems and recognized €2.3 billion revenue from 13 systems this quarter. Net system sales of €5.7 billion which was mainly driven by Logic at 63% and with the remaining 37% coming from Memory. Installed Base Management sales for the quarter came in at €1.6 billion which was higher than guided due to additional service and upgrade sales.

Gross margin for the quarter came in at 51.4% which is above our guidance, primarily driven by installed base business. On operating expenses, R&D expenses came in at €1.041 billion and SG&A expenses given at €284 million, both basically as guided. Net income in Q4 was €2 billion, representing 28.3% of net sales and resulting in an EPS of €5.21.

Turning to the balance sheet; we ended the fourth quarter with cash, cash equivalents and short-term investments at a level of €7 billion.

Moving to the order book; Q4 net system bookings came in at €9.2 billion which is made up of €5.6 billion for EUV bookings and €3.6 billion for non-EUV bookings. These values also include inflation corrections. Net system bookings in the quarter are more balanced between Logic and Memory relative to past few quarters, with logic at 53% of the bookings, while memory accounted for the remaining 47%.

Looking at the full year, net sales grew 30% to €27.6 billion, with a gross margin of 51.3%. EUV system sales grew 30% to €9.1 billion, realized from 53 systems while a total, we shipped 42 EUV systems in 2023. DPV system sales grew 60% to €12.3 billion. Our metrology and inspection system sales decreased 19% to €536 million.

Looking at the market segments for 2023; logic system revenue was €16 billion which is a 60% increase from last year. Memory system revenue was €6 billion which is a 9% increase from last year. Installed base management sales was €5.6 billion which is a 2% decrease compared to previous year. At the end of 2023, we finished with a backlog of €39 billion. Our R&D spending increased to €4 billion in 2023 as we continue to invest in innovation across our full product portfolio. Overall, R&D investments as a percentage of 2023 sales were about 14%. SG&A increased to €1.1 billion in 2023 which was about 4% of sales.

Net income for the full year was €7.8 billion, 28.4% of net sales, resulting in an EPS of €19.91. We finished 2023 with a free cash flow generation of €3.2 billion. We returned €3.3 billion to shareholders through a combination of dividends and share buybacks in 2023.

With that, I would like to turn to our expectations for the first quarter of 2024. We expect Q1 net sales to be between €5 billion and €5.5 billion. We expect our Q1 installed base management sales to be around €1.3 billion.

Gross margin for Q1 is expected to be between 48% and 49%. Lower revenue and margin relative to Q4 is primarily driven by lower emerging volume, along with an unfavorable change in product mix. In addition, we also expect EUV volume and lower installed base business in Q1 relative to Q4. The relatively slow start to the year is a reflection of the current state of the industry coming out of a downturn. As it relates to gross margin, I would like to make a few more comments on the 2024 margin drivers as well as our longer-term ambitions of 54% to 56% by 2025. We finished 2023 with a full year gross margin of 51.3% and there are a number of developments that could impact the gross margin in 2024.

For EUV, positive drivers include a higher ASP of the 3800E as well as improving EUV service margins. For DPV, we expect product mix to have a negative impact on margin in 2024. On our installed base business, we currently expect a similar gross margin as 2023 but the final impact will ultimately depend on the level of upgrades in 2024. And finally, as we have said before, we expect significant costs in 2024 related to the introduction of High-NA and to the ramp of our capacity to 90 EUV, 600 DPV levels that we have talked about before which will create pressure on the gross margin.

When we assess the combined effects of these different developments, we expect a slightly lower gross margin in 2024 compared to 2023. We are still targeting our earlier communicated gross margin ambition of 54% to 56% by 2025. This increase in gross margin will be driven by a number of items.

First, higher sales volume, both in EUV and DPV which improved fixed cost coverage. Second, a move to a higher-margin EUV 0.33 NA system as the vast majority of systems in 2025 are planned to be 3,800 E-Systems. Third, we expect reduced headwinds from capacity investments as we ramp volume, including high NA. Fourth, we will also be transitioning to a higher-margin EUV high NA system, the 5200 in 2025. Lastly, we expect our installed base business to have a positive impact on 2025 margins due to both improved EUV service margins as well as increased upgrade business volume.

The expected R&D expenses for Q1 are around €1.07 billion and SG&A is expected to be around €300 million. Our estimated 2024 annualized effective tax rate is expected to be between 16% and 17%. In Q4, ASML paid the second quarterly interim dividend of €1.45 per ordinary share. ASML intends to declare a total dividend for the year 2023 of €6.10 per ordinary share. The third interim dividend of €1.45 per ordinary share will be made payable on February 14, 2024.

Recognizing this third interim dividend and the 2 interim dividends of €1.45 per ordinary share paid in 2023, this leads to a final dividend proposal to the general meeting of €1.75 per ordinary share. In Q4 2023, no shares were purchased.
 
"Looking at the market segments for 2023; logic system revenue was €16 billion which is a 60% increase from last year. Memory system revenue was €6 billion which is a 9% increase from last year."

60% increase in logic? This must be from China.

"While we see some positive signs of recovery, we feel it might be a bit too early to change our perhaps conservative view as communicated last quarter and therefore, still stay with our previously communicated expectation of 2024 revenue to be similar to 2023."

I highly doubt that. Maybe single digit growth versus double. I do not think China is done.
 
Peter Wennink
Thank you, Roger. As Roger has highlighted, we had another year of very strong growth in a very challenging environment. And we finished the year with a solid backlog of €39 billion.

The uncertainty remains in the market due to a number of global macro concerns, while the semiconductor industry is currently working through the bottom of the cycle. Our customers are still not certain on the shape or slope of the recovery this year but there are some positive signs in the indicators that we have been monitoring. Industry end market inventory levels continue to improve, moving towards more healthy levels. Lithography 2 utilization levels are still running lower than normal but are now improving in both logic and memory. We expect utilization levels to continue to improve over the course of this year.

And lastly, as mentioned by Roger, we saw very strong order intake in the fourth quarter in support of future demand. To be able to follow the curve of the industry recovery, we are looking at the combined demand for 2024 and 2025. As mentioned last quarter, we fueled 2024 as a transition year in preparation with the expected strong demand in 2025. We, therefore, continue to make investment this year, both in capacity ramp and in technology to be ready for the upturn in the cycle.

While we see some positive signs of recovery, we feel it might be a bit too early to change our perhaps conservative view as communicated last quarter and therefore, still stay with our previously communicated expectation of 2024 revenue to be similar to 2023.

Looking at the market segments; customers are indicating they are seeing healthy growth this year, primarily driven by AI-related demand for both Logic and Memory but also expected from other end markets as inventory levels improve. And coming off a very strong year in 2023 with 60% growth in Logic revenue, we expect some pause in demand as customers digest the capacity additions and while utilization levels improve. Based on current demand, we see lower Logic revenue in 2024 versus 2023. For Memory, inventories are approaching normal levels and customers are expecting to see demand growth on a number of end markets this year.

Litho demand is primarily driven by DRAM technology node transitions in support of advanced memories such as DDR5 and HBM in support of AI-related demand. We currently see revenue growth in our 2024 memory business versus 2023.

Turning to our businesses for EUV; we are expecting revenue growth in 2024 and we are planning to recognize revenue on a similar number of EUV low-NA systems as 2023 which includes the fast shipments for 2023. Although we planned a similar number of systems as 2023, we will have higher ASPs from the NXE:3800E systems, more weighted towards the second half of the year. In addition, we expect revenue from 1 or 2 high-NA sectors.

Based on the aforementioned, we expect our non-EUV business to be down in 2024, primarily driven by lower immersion sales relative to 2023. For our installed base business, based on our view today, we expect a similar level of revenue compared to last year, plus the recovery becomes more clear this year. Customers may likely look to upgrade their systems in preparation for 2025. And this could provide future business opportunity this year.

As a reflection of the current state of the industry coming out of a downturn and an expected recovery over the course of 2024, we expect a stronger second half relative to the first half of this year.

On the geopolitical front, as communicated earlier, we do not expect to get export licenses for our most advanced immersion systems, the NXE:2000 and up for China in 2024. We have been in contact with the U.S. government on their export control regulations announced in October last year and we can confirm the estimated financial impact as communicated in October.

At that time, we stated the impact of the Dutch and the U.S. export control regulations combined is 10% to 15% of our 2023 China system revenue. This impact is based on our presumption that as of 2024, we will not obtain export licenses for NXE:2000 and up immersion systems to Chinese customers. And in the case of only a handful of Chinese fabs, this also includes NXE:1970 and 1980 systems. While the export regulations had an impact on our business, we continue to see strong demand for mid-critical and mature nodes in China.

Looking longer term, while there are still significant uncertainties, primarily driven by the macro environment, it appears we are passing through the bottom of this specific cycle and expect an industry recovery over the course of 2024. Based on discussions with our customers and supported by our strong backlog, we currently expect 2025 to be a strong year driven by a number of factors.

First, the secular growth drivers in the semiconductor end markets which we have previously discussed, such as energy transition electrification and AI. The expanding applications, along with increasing lithography on future technology nodes, drives demand for both advanced and mature nodes. Second, the industry expects to be in the middle of a cyclical upturn in 2025. And last, as mentioned earlier, we need to prepare for a significant number of new fabs that are being built across the globe in some instances clearly supported by several government incentive plans. These steps are spread geographically, are strategic for our customers and are scheduled to take our tools.

It is essential that we keep our focus on the future and build capacity in preparation for further long-term growth as we discussed in the market scenarios for 2025 and 2030 during our Investor Day in November 2022. We plan to update our view during our Investor Day this year on November 14, 2024.

In summary, although there are still near-term uncertainties with a positive outlook trend, we clearly remain confident in our long-term growth opportunity. And with that, we'd be happy to take your questions.
 
"In addition, we expect revenue from 1 or 2 high-NA sectors."

Which would be TSMC and Samsung. The question is how long will it take to get those systems into HVM? Maybe we will learn more at SPIE next month but from what I hear it is years not months.
 
"At that time, we stated the impact of the Dutch and the U.S. export control regulations combined is 10% to 15% of our 2023 China system revenue. This impact is based on our presumption that as of 2024, we will not obtain export licenses for NXE:2000 and up immersion systems to Chinese customers. And in the case of only a handful of Chinese fabs, this also includes NXE:1970 and 1980 systems. While the export regulations had an impact on our business, we continue to see strong demand for mid-critical and mature nodes in China."

This is aboveboard system shipment to China. In my opinion some of those systems will still make it into China. And what about system upgrades? Are they banned as well or just new systems?
 
On average per quarter, DUV immersion sales have been going up relative to EUV. I wonder if it has to do with China.

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Does anyone have a rough idea of how many duv tools are needed in mature nodes (28nm, 90nm, etc.) Doing some calculation, 30% of ASML 2023 revenue is from China roughly 8bn. US export control banned 10-15% advanced immersion tools which is around 1bn. So China ordered roughly 7bn dry DUV tools. Average ASP of dry DUV is 10m for 2023 so China basically ordered ~700 DUV tools. Just wondering what wspm capacity this could translate.
 
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"In addition, we expect revenue from 1 or 2 high-NA sectors."

Which would be TSMC and Samsung. The question is how long will it take to get those systems into HVM? Maybe we will learn more at SPIE next month but from what I hear it is years not months.
If the prototype tool installation and field accapetance take nearly a year, material/process qualification might take another year if going smoothly. I would bet the optimal HVM timeframe will be 2026/2027.
 
If the prototype tool installation and field accapetance take nearly a year, material/process qualification might take another year if going smoothly. I would bet the optimal HVM timeframe will be 2026/2027.

The challenge with EUV is throughput as that is what tells you how many EUV systems you must have for the number of wafers you will produce per month. An even bigger challenge is getting those EUV systems. In that regard, High-NA EUV could be years out for TSMC. Intel could certainly do it sooner since they make less wafers but the cost of High-NA EUV will be a problem. My guess is that TSMC will have High-NA EUV much sooner with Intel breathing down their necks. Same thing with backside power delivery which Pat mentioned on the Intel call multiple times. It is good to have competition, absolutely.
 
The challenge with EUV is throughput as that is what tells you how many EUV systems you must have for the number of wafers you will produce per month. An even bigger challenge is getting those EUV systems. In that regard, High-NA EUV could be years out for TSMC. Intel could certainly do it sooner since they make less wafers but the cost of High-NA EUV will be a problem. My guess is that TSMC will have High-NA EUV much sooner with Intel breathing down their necks. Same thing with backside power delivery which Pat mentioned on the Intel call multiple times. It is good to have competition, absolutely.
Daniel: The problem will be Hi-NA EUV maturity. Samsung and TSMC will get their prototype Hi NA EUV soon for the evaluation also. They are not waiting for maturity and adopting tools then. Indeed, the cost (2x tool price and need to prove 2x throughput to meet requirement) is a big problem. When we are reaching the patterning limit, 8nm (resolution spec for Hi NA) means there are around 16 Si atoms in a row*, which means we count atoms, and more challenges ahead for precise process control. Upon this, I would not expect further scaling and Hi-NA EUV might be used in very few layers. If BS-PDN, 3D package and chiplet ecosystem are ready in 2-3 years, then I will expect logic goes like 3D NAND which have no further scaling needed and no EUV layer in 3D VAND.


*The lattice constant of crystalline silicon, which has a diamond cubic crystal structure, is approximately 0.543 nm (or 5.43 Å).
 
Daniel: The problem will be Hi-NA EUV maturity. Samsung and TSMC will get their prototype Hi NA EUV soon for the evaluation also. They are not waiting for maturity and adopting tools then. Indeed, the cost (2x tool price and need to prove 2x throughput to meet requirement) is a big problem. When we are reaching the patterning limit, 8nm (resolution spec for Hi NA) means there are around 16 Si atoms in a row*, which means we count atoms, and more challenges ahead for precise process control. Upon this, I would not expect further scaling and Hi-NA EUV might be used in very few layers. If BS-PDN, 3D package and chiplet ecosystem are ready in 2-3 years, then I will expect logic goes like 3D NAND which have no further scaling needed and no EUV layer in 3D VAND.


*The lattice constant of crystalline silicon, which has a diamond cubic crystal structure, is approximately 0.543 nm (or 5.43 Å).

I agree. EUV was the same. I do not remember how long it was from the time TSMC had the first EUV system to the time it was in full use for HVM. I think TSMC N5 was the first process with double digit EUV layers. Maybe it was N6. If I had to pick a date for TSMC to have full HIGH-NA EUV I would guess 2030. They may have a few layers before then ( like N7+ ) but not what we would call full usage.
 
Daniel: The problem will be Hi-NA EUV maturity. Samsung and TSMC will get their prototype Hi NA EUV soon for the evaluation also. They are not waiting for maturity and adopting tools then. Indeed, the cost (2x tool price and need to prove 2x throughput to meet requirement) is a big problem. When we are reaching the patterning limit, 8nm (resolution spec for Hi NA) means there are around 16 Si atoms in a row*, which means we count atoms, and more challenges ahead for precise process control. Upon this, I would not expect further scaling and Hi-NA EUV might be used in very few layers. If BS-PDN, 3D package and chiplet ecosystem are ready in 2-3 years, then I will expect logic goes like 3D NAND which have no further scaling needed and no EUV layer in 3D VAND.


*The lattice constant of crystalline silicon, which has a diamond cubic crystal structure, is approximately 0.543 nm (or 5.43 Å).
Imec doesn't expect any 3D stacking until like 2030-32. So while I think we will get to a NANDification of logic eventually. That doesn't sound to be happening until the mid 2030s at the earliest since TSMC has been pretty consistent that CFET then 2D then 1D for their 10+ year roadmap. As for high-NA I don't think it is about pushing to 8nm features (low-NA can't even do the 13nm). Fred, Tanj, and I were talking about this earlier. Since I don't want to put words in their mouths the TLDR of my thoughts was that the main application would be reducing multi patterning for middle layers rather than pushing min feature. For example doing something like N5's 30nm SALELE M0 with high-NA DP. If memory serves from a Nikon paper I read while ago they mentioned that DUV double patterning cost ranged from like 3-4x the cost of DP (depending on the scheme used) because you need at least 2x more litho, a bunch of extra non litho tools, and you drastically lower cycle time. Back to high-NA; if all you try to do is reduce the degree of multipatterning, now you only need the cost of a high-NA exposure to be to be like 2-3x the cost of low-NA exposure (adjusted the multiplier down because EUV is more expensive then DUV) for the fab to get a positive ROI.

I agree. EUV was the same. I do not remember how long it was from the time TSMC had the first EUV system to the time it was in full use for HVM.
I think it was like 2015 or 2016 was when the fist sudo HVM customer tools started being delivered. With the first sort of real HVM tools going to Samsung/TSMC in like 2017-2018 timeframe. Granted this is a smaller transistion then EUV so it seems we are skipping a lot of the growing pains of 2015-2018 since ASML claims like 200wph rather than the like 60wph for the 2015 tool.
I think TSMC N5 was the first process with double digit EUV layers. Maybe it was N6. If I had to pick a date for TSMC to have full HIGH-NA EUV I would guess 2030. They may have a few layers before then ( like N7+ ) but not what we would call full usage.
Samsung 7LPP might have been first to double digit layers since they were fully EUV rather than just having it there as a side thing for yield learning like with N7+. Granted the throughput and or yield were so bad (my guess is mostly column A with some column B) that if memory serves it was practically vaporware until when N6/N5 were starting to rollout... Buuuut that's Samsung for you.
 
The High-NA doesn't address the stochastic patterning which is already serious for 5nm. Looks like they should focus on speeding up the quadruple patterning instead.
 
The High-NA doesn't address the stochastic patterning which is already serious for 5nm. Looks like they should focus on speeding up the quadruple patterning instead.
Fred: tsmc ran could be more than 1 million 5nm wafers with good yield till now. The stochastic effect could be serious but tsmc has fixed it already in 5nm. It seems you do not favor EUV since day one but the sun still arises from the East every day. The stochastic effects can not be scaled. It will be even worse for smaller features to be printed using HiNA EUV. Go for these smart engineers.
 
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Fred: tsmc ran could be more than 1 million 5nm wafers with good yield till now. The stochastic effect could be serious but tsmc has fixed it already in 5nm. It seems you do not favor EUV since day one but the sun still arises from the East every day. The stochastic effects can not be scaled. It will be even worse for smaller features to be printed using HiNA EUV. Go for these smart engineers.
I don't think TSMC would be using EUV with its stochastic issues. 5nm with larger pitches and double patterning with SALELE, even there, there is some risk, though less obvious than with direct print.
 
Looks like they should focus on speeding up the quadruple patterning instead.
I mean that is mostly out of ASML's hands. They would need faster EFEMs, faster AMHS, faster and more precise deps/etches. Only thing they can do is improve throughput to slightly make it faster or lower EPE/LER for better CDs. Unless you mean speeding up low-NA tools and using low-NA triple or quad pattering vs high-NA SALELE?
 
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