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Samsung and IBM have come out with a VTFET transistor structure that they claim is far more energy efficient and can be much more space efficient. Any thoughts or comments would be appreciated.
IBM and Samsung have unveiled a new semiconductor chip design they say can enable the continuation of Moore's Law. The breakthrough architecture sees transistors built onto the chip in a way that allows for vertical current flows, resulting in a more densely packed device and paving the way for…
When shrinking the active width or gate width, the current is being shrunk, without possible compensation by vertical extent. Lg can be changed vertically, but it's not as simple a knob.
Two factors having me doubting the vertical FET (and this has been for years...).
1) at the end of the day the problem of density in logic (VNAND is a different structure) is how to place three contacts on a plane and
2) how to have a W that allows enough current to drive the line at the L you can get away with (W is always > L).
For 1) vertical or horizontal structures have no real difference, for 2) FinFET and nanosheets are great because the W is hidden in the vertical direction and/or the number of sheets/fin. Vertical brings W back to the plane as it is the perimeter of the structure and electrostatic control impose well defined limits on aspect ratio or diameter.
So I still wait a real peer reviewed paper to see how they did it.
(edited: sorry Fred, we probably wrote it at the same time and we are saying the same thing)
Yes, that's a subtle tradeoff as well. Indeed, the three contacts must be patterned separately since they are not in the same plane.
But the footprint of the the three terminals could be smaller, in the sense that the source and drain can be placed closer together laterally, from top view. The gate contact is still offset but that is how it is now with FinFETs.
Starting withthe obvious...
I have no knowledge of what Samung/IBM are doing; however, if we believe the basic premise about size reduction - clearly smaller cells would of themselves reduce parasitic delay and dissipation.
The question remains as to how that virtuous circle might be achieved?
Could there be mileage in the combination of vertical asymmetry and self-aligning gate-all-round allowing shorter channels and higher current densities?
All is in the proportionality of the different variables. Reducing size typically increase R, C is a strange beast and depends on materials and topology, at that point you rely on I increasing enough to compensate. Vertical symmetry bring you nothing at device physics level compared to horizontal wires/sheets the moment you have Gate All Around. Actually vertical will introduce a dissymmetry between the top contact and the bottom one that will have different paths to the metal line.. You may want to look in papers published over the years by JP Colinge studying the various effects and geometries (he was talking about GAA at the end of the eighties ...) and in papers at IEDM and VLSI.
And is the reason why we need reviewed papers and not marketing announcements in order to have an evaluation. Why they didn't submit to IEDM ? We will see how real it is at next VLSI if they play.
Increasing Weff/Leff and getting more drive current per unit area doesn't help if the contact resistance -- especially to S/D -- goes up, this parasitic resistance then limits gain and drive current.
We've seen this effect getting bigger and bigger as FinFET processes shrink, at 5nm it's one of the main factors limiting transistor performance. It'll only get worse with nanosheet transistors with even higher channel density than FinFETs.
So a transistor architecture like VTFET which crams a lot of gate/channel (higher capacitance) into a small area but with lousy access resistance won't show the hoped-for performance improvements, in fact if could well be worse.
Yes for the VDD/VSS connection (assuming both are buried or use the substrate), but this doesn't help as soon as you have gates or circuits with series transistors, meaning a lot of them including D-types and RAMs.
Yes for the VDD/VSS connection (assuming both are buried or use the substrate), but this doesn't help as soon as you have gates or circuits with series transistors, meaning a lot of them including D-types and RAMs.
Clearly everything can be done in dynamic logic without using series gates, but naturally the overhead would preclude doing this in normal arrangements. Maybe there are situations where the value exceeds the cost?
Despite the mainstream media hype about IBM’s Vertical-Transport Nanosheet announcement at IEDM, we believe it is IBM’s work on perfecting HNS processes is more likely to have an impact on the industry. pFET channel mobility, volume less Vt solutions and high voltage I/O solutions address problems the industry is currently wrestling with for the FinFET to HNS transition
newatlas.com
