You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!
Have you looked at the portfolio of EM images of the result of the tool? They have a 20:1 directional etch and do not ruin the endwall when they extend. It also has some interesting side effects like 90% reduction in bridging, and they show a variety of other creative uses for the tool.
You should give them some credit for doing their homework, not just slam it as equivalent to some research papers of the past. Looks to me like they have added a new, useful tool to the toolbox in the fab, and they have got some pretty clean results to show.
The 20:1 is horizontal in this case. It seems likely both the plasma flow and the chemistry (both plasma and resist) has been tweaked to get there.
What did they mess up in the double patterning? If you are creating a layer with 1D structures and your goal is to avoid tip to tip distance limitations, this allows you to sidestep that. The only gotcha would be if the litho-friendly geometry would be short enough to give a shadow, but that seems like a rule the EDA can handle with marginal effect on density.
I would love to understand the implications that this could have on fabs demand for EUV. The presentation seems to only show use case for oval patterns, so curious how many EUV layers for N3 will this be technology be relevant for.
I would love to understand the implications that this could have on fabs demand for EUV. The presentation seems to only show use case for oval patterns, so curious how many EUV layers for N3 will this be technology be relevant for.
Unless TSMC provisioned for it years in advance and designed the layers that are only just barely double patterned for an easy swap to single exposure, it cannot be done after the fact economically. Given the fact TSMC reduced the number of EUV double patterned layers with N3 and N3E over time, it seems plausible they didn't make these provisions due to being a bit too bullish on the economics they could achieve with their current lithographic capabilities.
The 20:1 is horizontal in this case. It seems likely both the plasma flow and the chemistry (both plasma and resist) has been tweaked to get there.
What did they mess up in the double patterning? If you are creating a layer with 1D structures and your goal is to avoid tip to tip distance limitations, this allows you to sidestep that. The only gotcha would be if the litho-friendly geometry would be short enough to give a shadow, but that seems like a rule the EDA can handle with marginal effect on density.
I would love to understand the implications that this could have on fabs demand for EUV. The presentation seems to only show use case for oval patterns, so curious how many EUV layers for N3 will this be technology be relevant for.
It's seems more presented as being an alternative to High-NA EUV, when actually they are competing against cutting. But in fact, ovals don't have a well-defined CD to base on. Straight features have the edge which can be preserved.
Unless TSMC provisioned for it years in advance and designed the layers that are only just barely double patterned for an easy swap to single exposure, it cannot be done after the fact economically. Given the fact TSMC reduced the number of EUV double patterned layers with N3 and N3E over time, it seems plausible they didn't make these provisions due to being a bit too bullish on the economics they could achieve with their current lithographic capabilities.
The lower metals, vias had much smaller pitch, so were not single patterned. The middle layers appear to have been converted to single, maybe relaxed pitch or simpler layout.
Given that rounded features are more sensitive to such random deformation errors, since the edge plays a larger role, it would seem to aggravate the issue.
It's seems more presented as being an alternative to High-NA EUV, when actually they are competing against cutting. But in fact, ovals don't have a well-defined CD to base on. Straight features have the edge which can be preserved.
First printing straight lines, then cutting them (blocking some portions from etching) into individual shorter strips. The strips are guaranteed straight.
A bit of marketing hyperbole...just a selective etch tool..not a "patterning" tool...not enabling, just cheaper...only replaces some, limited double patterning..similar to other existing technology...can only "etch" what EUV "patterns"......https://conta.cc/3YmtxFk
AMAT isn't really addressing the tip-to-tip or starting feature lithography difficulty. Also, Intel is claiming to want bidirectional metal layers, how would this work for them.
The lower metals, vias had much smaller pitch, so were not single patterned. The middle layers appear to have been converted to single, maybe relaxed pitch or simpler layout.
That was my point (although it was probably poorly articulated). The lower metals were already locked in stone and the middle layers got hasty conversions to larger pitchs. If TSMC planned to insert this tool into their process flow to replace double patterned layers with LEE layers on N3E, I don't think we would be seeing such a substantial density hit. But who knows I could totally be off base here and maybe that is exactly what happened.
AMAT isn't really addressing the tip-to-tip or starting feature lithography difficulty. Also, Intel is claiming to want bidirectional metal layers, how would this work for them.
Maybe they are using paternshapping for lower metal vias (if that is even plausible for this technology)? Unless my understanding of the tech is wrong, I assume you can use it for removing bridge defects even with birectional rules given how short that etch probably is relative to a pattern shaping etch? Put another way maybe the bridges are small enough that the ion ribbon can cut it and scan past before it meaningfully upsets the intended pattern shape. But that is way beyond my knowledge so I am curious what you think of my hairbrained idea?
Maybe they are using paternshapping for lower metal vias (if that is even plausible for this technology)? Unless my understanding of the tech is wrong, I assume you can use it for removing bridge defects even with birectional rules given how short that etch probably is relative to a pattern shaping etch? Put another way maybe the bridges are small enough that the ion ribbon can cut it and scan past before it meaningfully upsets the intended pattern shape. But that is way beyond my knowledge so I am curious what you think of my hairbrained idea?