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Intel 10nm process problems -- my thoughts on this subject
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platinumjsi
New member
If I understand this correctly Intel is going to walk the 10nm process back to 12nm? Why wouldn't they just walk the 14nm process down to 12nm like TSMC and Samsung? This make no sense to me.
14nm 16nm 10nm and 7nm - What we know now
Scott is on vacation, I will ask him when he returns. Or maybe IanD can comment?
Scotten Jones
Moderator
I looked at the write up, I do not find the claims that Intel is walking the process back to 12nm credible. I believe the pitches I have previously disclosed continue to be correct.
platinumjsi
New member
Im interested to see how it plays out, intersting times ahead.
Daniel and Scotten
i think there is a possibility to the theory that Intel might be relaxing on some of the pitches esp M0 and M1. Scotten wrote that Intel used SAQP on M0(36nm) and M1(40nm) while TSMC and GF used SADP for M0(40nm). Its possible that Intel is now relaxing M0 and M1 to 44nm to go with SADP as Intel's 10nm M2 is 44nm and uses SADP.
There is also a public roadmap which talks of a 10++ process with a rearchitected metal stack. I would like to hear Scotten's opinion on what this so called rearchitected metal stack could mean and the amount of effort needed. My understanding is this involves significant changes to metal stack esp M0 and M1 and is being done to help with yield issues.
https://www.eetimes.com/document.asp?doc_id=1332527&page_number=2
I hope both of you have been able to read the full article by Charlie but I think Intel's 10nm which finally makes it to HVM by late 2019 or early 2020 will not be the one they pitched at IEDM 2017. Anyway its going to be interesting to see a techinsights teardown of Icelake client CPUs whenever they launch.
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DrizztVD
Guest
Lol, semantics. If you walk 10nm up or 14nm down to 12nm, don't you end up with exactly the same thing? This is beside the point.
Without someone having access to the whole article by Semiaccurate, it is difficult to know what the real claims are. Saying "12nm" has very little objective meaning. IMO, this is a slight walking back to closer to "8nm" or even "7nm" but not "7nm+" when compared to the way foundaries are calling things.
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DrizztVD
Guest
I'd like to see Intel stumble just for hurting AMD back in the day when they forced exclusive partnerships on OEMs. The fine for that took 10+ years to be paid out to AMD (not even settled completely yet), given how Intel (and any other company) just does appeal after appeal into infinity to delay justice and maximise the damage they did to AMD.
This is where one calls "justice" in the way one loses a point in a game after gaining one unfairly.
To be clear, having PCs with Intel 10nm inside on the shelves by the end of 2019/2020 is not the same as Intel HVM in 2019/2020. Intel will be making an announcement tomorrow so lets talk more after that:
Intel Webcast Events
So Client by EOY 2019 and server in mid'20. So HVM in H1'19 perhaps?
I just found that this Intel 10nm processor (https://ark.intel.com/products/136863/Intel-Core-i3-8121U-Processor-4M-Cache-up-to-3-20-GHz-) is already being sold in Intel's own NUCs: https://ark.intel.com/products/seri...PC-with-8th-Generation-Intel-Core-Processors; the PC is listed around $500. The processor transistor density is listed by TechInsights as 100.8 MTr/mm2: Intel 10 nm Logic Process
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This is the "crippled 10nm marketing CPU" that I was referring to earlier:
Is Intel's upcoming 10nm 'launch' real or a PR stunt? - SemiAccurate
It's slightly slower than the equivalent 14nm parts and has the same 15W TDP even though the integrated graphics doesn't work -- if you read the NUC specification carefully it says "Integrated Graphics -- yes" (which means "no separate graphics card" -- obviously impossible in a NUC) but then says "Discrete graphics -- Radeon 540". The giveaway is the 45mm x 24mm package size for the CPU, which probably means there's a separate AMD graphics chip in the same package as the Intel CPU (with non-functional graphics).
The reason Intel are not promoting this CPU is that it's frankly rubbish, inferior to its 14nm predecessors, and shows their 10nm process in a very negative light not a positive one. It seems that they only released one batch of about a hundred thousand parts for use in a few low-key laptops/tablets/NUCs, with no more 10nm product planned until the promised IceLake launch in 3Q2019. It's purely a marketing/PR device so that Intel can say "10nm is in production" and analysts who have no idea about technology will get off their backs because "Hooray, Intel 10nm finally works".
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The two 10nm parts were 15 W TDP while the 14nm parts had one 65 W, the other 100 W TDP.
The AMD Radeon is listed separate for all 4 parts. The 10nm parts had lower GHz than the 14nm, so indeed lower performance.
It seems that TSMC N5 has 14 EUV layers (5 for N7+), so the new 5nm fab will need something like 17 EUV steppers with the above calculations. Isn't it obvious that 5nm is really going to need 1 EUV stepper per EUV layer, because anything else is a logistical nightmare? This means ASML have to get the source power up to about 300W, which should be achievable.
Huh? For the parts referred to in the quoted post, the 8120U (10nm, no GPU) is 15W TDP with 2.2GHz/3.2GHz base/turbo, the 8130U (14nm with GPU) is 15W and 2.2GHz/3.4GHz.
Oh, I was quoting the second ark.intel.com link: https://ark.intel.com/products/seri...PC-with-8th-Generation-Intel-Core-Processors;
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It's going to be complicated by mask count:
View attachment 22449
This is from the DAC 2018 TSMC/ARM/Synopsys Breakfast video of the presentation by TSMC: DAC 2018 TSMC/Arm/Synopsys Breakfast
I'm not sure what you mean; TSMC have said there are 14 EUV layers (MEOL+BEOL up to M6?) in N5, all the rest are immersion as normal.
If we take N7 to have 80 masks and N7+ replaces 15 of these by 5 EUV layers this gives 65 immersion plus 5 EUV -- so similar wafer cost and NRE to N7 since an EUV mask costs about 3x an immersion mask. N5 has 14 EUV which from the graph means N5 must have something like 65 immersion + 14 EUV (79 total) -- so about the same number of immersion masks as N7+ but 9 extra EUV masks, which means costs (wafer and NRE) will be significantly higher.
If you have a fab line it's difficult to run unless you have 1 EUV stepper (or 2 -- any integer works) per EUV layer -- for example how does having 5 steppers per 4 layers work? So if N5 has 14 EUV layers, I'd expect the TSMC 5nm fab to have at least 14 EUV steppers -- or given the availability, maybe a couple of spares so that 14 are in use and 2 undergoing maintenance at any one time. This would fit pretty well with the stated fab capacity if the source power is 300W.
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So the way I was considering it was 4 EUV layers would remove 2 masks per layer or 8 masks total for N7+ while 14 EUV layers would remove 28 masks for N5, compared to N7. It doesn't look that way in the graph. So I conclude that there was some multipatterning going on even for EUV. Actually the recent article on TSMC OIP forum https://www.semiwiki.com/forum/cont...open-innovation-platform-ecosystem-forum.html mentions something to that effect, that M1 has multipatterning color assignment.
Nope, there are just more immersion layers in N5 because the process is more complex -- at 5nm all EUV layers are single-patterned.
The M1 multipatterning referred to is not because of double-patterned EUV, it's because of the 3:2 ratio between poly pitch (underlying cell) and metal pitch (port connections). This means there are (I think) 4 versions of each cell with different port positions and restrictions about which version of a cell can be next to which version of the adjacent cells, and the tools deal with this by using colouring.