5nm Chips? Yes, but When?

For any invention, technical proof of concept or prototyping happens years ahead of the invention being infused into actual products. When we talk about 5nm chip manufacturing, a test chip was already prototyped in last October, thanks to Cadence and Imec. Details about this chip can be found in a blog at Semiwiki (link is given at the end). So, where is the technical wall for Moore’s law? Yes, it’s retarding, but is it the end? When can we expect 5nm commercial chips?

Not a single week passes without hearing about Moore’s law – Moore’s law is dead, Moore’s law long live, More than Moore, Steps to keep up Moore’s law….. We have to realize one thing that all the dots have to connect together for making a particular technology, process, product, or service to become successful.

Often discontinuities arise in different forms in any established technological or business process. In transistor density scaling on silicon, we saw one after 28-22 nm nodes; after a brief pause, in technical terms it needed a structural change in transistors to go below 20 nm when FinFET arrived, and now FD-SOI is also a contender. FinFET has extended till 10nm. Below 10nm, we are again debating on whether FinFET should extend further or it should take another structural change in transistor – nanowire FET (Gate-All-Around).

There are pros and cons for each alternative; availability of EUV can simplify lithography and reduce cost to a certain extent, what if EUV is not there in time (it’s been already delayed according to technology evangelists), should we extend the 193nm immersion technology but that increases cost and complexity. It’s visible, what worked from 180nm to 28nm linearly is not working in the same fashion below that. Below 22nm discontinuities are more frequent after every couple of nodes. New solutions have to arrive.

Now let’s see the connection of dots; technology, business, economy, technology consumption pattern, and the future scenario. Here, we can find business level discontinuity (w.r.t. silicon density scaling) which indirectly affects technology roadmap.

What Moore’s law has provided us so far seems good enough for a good number of years from now. The technology which appears to witness maximum traction at this juncture is IoT, and 28nm seems good enough for IoT from all angles (performance, power, cost,…). Automotive is fine with 28nm and above. Same stands true for other segments such as home, personal, industry, and so on. These are business level discontinuities for silicon density scaling. Smartphones with current technology and 4G, and upcoming 5G would be more than enough in terms of performance, data processing, and so on. We are seeing slowdown in Smartphones, the largest driver of semiconductors. Where do we need super-duper high-end device needing 5nm? And who can afford it, because it’s going to be hugely expensive? We need to first consume what we have. Let’s look at the other aspects.

An IC Insights report on worldwide semiconductor R&D growth says that the industry-wide R&D expense grew by just 0.5% in 2015 and the growth in R&D expense by top10 R&D spenders stood at 2%. Although Intel is the top R&D spender amounting to 22% of total worldwide semiconductor R&D expense, Intel’s R&D expense in 2015 grew by 5% compared to its average R&D expense growth of 13% since 2010.

Now look at in which areas world’s major investment is flowing today, it’s not semiconductors –

Top areas for venture capital investment are Software, Biotechnology, Media & Entertainment, IT services…. semiconductor comes way down the line beyond 10[SUP]th[/SUP] rank.

What’s the future outlook for semiconductors? Again, another IC Insights report says in 2016 worldwide IC Market growth will remain between 2 to 6%, 4% being the mid-point. It cautions, tendency of growth going down is more than going up, of course taking into account worldwide financial stress and more or less deflationary trend.

Combining all these factors together what I can envision is that couple of years from now, the ecosystem, the broader community is asking the semiconductor community to provide what they have – 14nm, 28nm, 45nm, doesn’t matter what it is, integrate them together heterogeneously in a system along with MEMS (and FPGAs) and show us it solves our purpose with minimum cost, lowest energy consumption, good enough performance, good configurability, safe and secure, automating and innovating our existing premises. The focus is on products and systems rather than semiconductor technology process. That’s one of the reasons why software comes at the top in VC investment because software connects things together securely and safely.

So, how do you see the future of semiconductor technology progressing? Do not forget, there has been massive consolidation (in one way attributed to financial stress), that will give way to innovation in future. While the semiconductor process innovation goes on, the broader community has to consume what they already have on their plate; in different forms of innovation at the system level using the existing process technology. Commercial proliferation of new semiconductor technology will be slow. In my view, I do see 5nm chips coming at some point of time, but not before mid next decade.

For 5nm test chip read the blog: IMEC and Cadence Disclose 5nm Test Chip

Pawan Kumar Fangaria
Founder & President at www.fangarias.com