You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!
As semiconductors continue to scale, designers are turning to 3DIC architectures to meet increasing demands for performance, energy efficiency, and functional density in data centers and edge AI applications. However, stacking multiple dies introduces new multiphysics challenges including electrical, structural, and thermal issues. Join this webinar to learn how RedHawk-SC Electrothermal enables designers to analyze …
Abstract Dive into the future of Bluetooth audio with Ceva and Dolphin Semiconductor’s breakthrough 12nm Smart Edge AIoT SoC solution. This webinar shows how advanced wireless connectivity, integrated AI processing, and premium audio technologies and power management come together to deliver superior performance, lower power, and faster time to market. Learn how a combined Ceva …
As power integrity challenges increase with advanced nodes and multi-die architectures, EMIR analysis must evolve beyond traditional signoff. In this Synopsys webinar, we will show how RedHawk-SC is expanding its capabilities not only to enhance EMIR analysis, but also to enable IR-aware Static Timing Analysis (IR-STA) and IR-driven ECO (IR-ECO) flows. Join us to learn how tighter integration …
Data rates have doubled, but validation methods have not kept pace. As PCIe, DDR, and multi-terabit optical interconnects evolve, engineers are encountering signal integrity challenges much earlier in the design process. Join Niels Fache, Senior Vice President and General Manager of Design Engineering Software at Keysight, to explore where validation becomes more challenging as speeds …
In this webinar, Intel will present how EMIB-T (Embedded Multi-die Interconnect Bridge with TSVs) enables compact, cost-effective multi‑die design while sustaining the bandwidth and power efficiency required for AI and datacenter designs. Intel will share a production-oriented EMIB-T reference methodology built on Synopsys' 3DIC Compiler platform that spans early planning through signoff. The webinar highlights how early bump …
As systems move into higher frequencies and wider bandwidths, small measurement errors can lead to costly design decisions. Engineers working in wireless, radar, satellite, and optical domains must now validate signals that push existing tools to their limits. Join Jun Chie, Vice President of Product Management at Keysight, to explore where measurement fidelity begins to …
Featured Speaker: Victoria Kolesov, Principal Engineer, Intel In this Synopsys webinar, Intel will present how its disaggregated designs across client and server platforms have driven the evolution of robust 3D multi-die design construction and signoff methodologies. Intel will share practical experience using Synopsys’ complete design implementation and signoff flows for static timing analysis signoff and …
AI data center networks now operate at a scale where device-level validation no longer reflects real performance. Engineers must understand how systems behave under realistic traffic conditions, not just in isolated tests. Join Ram Periakaruppan, vice president and general manager of network applications and security at Keysight, to learn how large-scale traffic emulation reveals congestion, …
As 5G and future 6G networks increase RF front-end complexity, acoustic wave filters and RF front-end modules are facing growing demands for higher frequency operation, wider bandwidth, lower losses, better thermal stability and deeper integration. Based on KnowMade’s latest analyses of RF Acoustic Wave Filters and RF Front-End Modules & Components, this seminar will explore how patent activity up …
*Company Email Required for Registration* Full-chip SoC debug has become one of the most expensive bottlenecks in modern verification. A single production issue can pull multiple engineers away days as they chase a failure through waveforms, logs, and across hundreds of thousands of lines of code. In this webinar, we will demonstrate how the Bronco …
As semiconductor complexity increases and board designs become denser, manufacturing teams face tighter tolerances, reduced test access, and rising pressure to maintain yield and throughput. Validating RF performance and high-speed digital signal integrity at production scale adds a new layer of complexity that traditional approaches struggle to address. Join Jason Kary, Senior Vice President and …
In this webinar with eShard, we dive into one of the most pressing questions in the community: Are physical attacks practical against post-quantum schemes in the real world? If yes, how to harden the code or the hardware? We’ll explore: How can cryptographic algorithms and their implementations be targeted by physical attacks? Leveraging a novel …
About this event This presentation provides a high‑level overview of how the updates in the 2026 Keysight Optical Design Engineering (ODE) product releases address emerging application areas, such as AR/VR systems, metamaterials, imaging and illumination design, and the evolving roadmap toward a unified platform for photonic integrated circuit (PIC) design. Updates featured come from CODE …