Webinar: Centralized Register Design and Verification from a Golden Specification

Online

Description Learn how to bring the ease of a document editor to your system architects and designers to create an executable specification using IDesignSpec™. This specification fully describes and documents your design and automatically generates all downstream views. Time Aug 18, 2022 10:00 AM in Pacific Time (US and Canada) REGISTER HERE

Austin Verification Seminar

Hotel Granduca Austin 320 South Capital of Texas Highway, West Lake Hills, TX, United States

Overview Delivering high product quality without sacrificing today’s demanding product schedules means boosting verification productivity and cutting bug escapes. Product development teams must speed time to coverage closure, requiring new and improved technologies that make a meaningful difference in a verification cycle. Agenda 9:00 - 9:30 Arrival and check-in Introductions and networking with your peers. …

Webinar: Scalable, On-Demand Verification to Reach Coverage Closure – The New Reality in Verification on the Cloud

Online

Synopsys Webinar | Wednesday, September 14, 2022 | 10 a.m. Pacific Verification has long been the most time-consuming and often resource-intensive part of chip development. Building out the infrastructure to …

Webinar: Achieving the Best Verifiable QoR using Formal Equivalence Verification for PPA-Centric Designs

Online

Synopsys Webinar | Tuesday, September 20, 2022 | 10 a.m. Pacific Synopsys Fusion Compiler offers advanced optimizations to achieve the best PPA (power, performance, area) on today’s high-performance cores and interconnect designs. However, advanced transformation techniques available in synthesis such as retiming, multi-bit registers, advanced datapath optimizations, etc. are of little value if they cannot …

Webinar: Improving Efficiency and Quality of Verification Environments with Automation

Online

Synopsys Webinar: Tuesday, October 18, 2021 | 10 a.m. Pacific REGISTER HERE Bugs can be introduced at any stage in the hardware design development process and escape into tapeout if the verification environment is unqualified. Measuring and improving verification effectiveness to prevent bugs during functional verification is the key to taping out bug-free high-quality designs. …

DVClub Europe Meeting: RISC-V Verification Strategies

Online

Tuesday 29th November, 2022 12:00 – 13:30 GMT FREE to attend Online RISC-V Verification Strategies With the popularity of the RISC-V open architecture, many companies are looking for Verification Strategies for developing their own cores or how to verify their integration into a subsystem or SoC. About DVClub The principal goal of each DVCLUB meeting is to …

Webinar: Code Review for System Architects

Online

* Company email is required* Register management tools have been used mostly in a bottom-up approach. There are some documents and/or spreadsheets created by the System Architects that are delivered to the design and verification teams. They then start capturing the HW/SW interface of the peripheral IPs in their in-house or commercial register management tool …

CadenceTECHTALK: Low-Power Verification Using Xcelium Simulation

Online

Don’t let power-related issues that appear late in the verification cycle impact your project schedule. Register for a webinar that shows you how to catch low-power issues early on. The Cadence low-power solution considers power at every step of the design flow, from architecture to functional verification, analysis, implementation, and signoff. This webinar will focus …

Synopsys VC Formal DPV Virtual Workshop Series Day 2

Online

Day 1 (February 1, 2023) of this workshop series will cover practical knowledge of the best datapath verification strategies and provide hands-on experience with the industry's best-in-class datapath validation app – Synopsys VC Formal DPV. This workshop includes a featured session presented by Theo Drane, Datapath Architect at Intel, who will share his experience on how …