Synopsys Webinar | Thursday, June 23, 2022 | 10:00 - 11:00 a.m. Pacific Today’s million gates integrated circuits (ICs) involve various intellectual properties (IPs) interfacing with each other through multiple …
Continue reading "Constraints-Driven CDC and RDC Verification Including UPF Aware Analysis"
Abstract: OSVVM has grown tremendously over the last couple of years. This period saw simulator independent scripting, test reporting, model independent transactions, virtual transaction interfaces, and additional verification components, each …
Continue reading "Advances in OSVVM’s Verification Data Structures (US)"
Synopsys Webinar | Wednesday, July 27, 2022 | 10:00 a.m. Pacific Analyzing the thousands of failures from daily regression runs is a manual, tedious, and error-prone process. The process can significantly impact quality-of-results, time-to-results and cost-of-results. The Synopsys Verdi® Regression Debug Automation (RDA) is an artificial intelligence (AI) driven verification technology for automating the process …
Continue reading "AI-Driven Verification: Saving Time with Verdi Regression Debug Automation"
Description Learn how to bring the ease of a document editor to your system architects and designers to create an executable specification using IDesignSpec™. This specification fully describes and documents your design and automatically generates all downstream views. Time Aug 18, 2022 10:00 AM in Pacific Time (US and Canada) REGISTER HERE
Overview Delivering high product quality without sacrificing today’s demanding product schedules means boosting verification productivity and cutting bug escapes. Product development teams must speed time to coverage closure, requiring new and improved technologies that make a meaningful difference in a verification cycle. Agenda 9:00 - 9:30 Arrival and check-in Introductions and networking with your peers. …
Overview As verification tasks become more and more challenging and complexity increases, we find ourselves looking for more advanced techniques and solutions to improve and shorten this task. Come and join us at CadenceCONNECT: Verification Day to learn about the latest updates on the advanced verification solutions that include the Perspec System Verifier, System VIP, …
Synopsys Webinar | Wednesday, September 14, 2022 | 10 a.m. Pacific Verification has long been the most time-consuming and often resource-intensive part of chip development. Building out the infrastructure to …
Synopsys Webinar | Tuesday, September 20, 2022 | 10 a.m. Pacific Synopsys Fusion Compiler offers advanced optimizations to achieve the best PPA (power, performance, area) on today’s high-performance cores and …
Summary Emerging 2.5D and 3DIC packaging technologies enable more design complexity, and bring some new verification challenges. We look at how to scale your verification capability to match and how to plan ahead for verification of die-to-die interconnect protocols such as UCIe and memory verification with HBM. Packaging technologies for 2.5D and 3DIC are becoming …
Synopsys Webinar: Tuesday, October 18, 2021 | 10 a.m. Pacific REGISTER HERE Bugs can be introduced at any stage in the hardware design development process and escape into tapeout if the verification environment is unqualified. Measuring and improving verification effectiveness to prevent bugs during functional verification is the key to taping out bug-free high-quality designs. …
Time: 09:00 BST / 10:00 CEST / 11:00 EEST and Israel / 13:30 IST The Cadence low-power solution considers power at every step of the design flow, from architecture to …
Continue reading "Cadence TECHTALK: Low-Power Verification using Xcelium Simulation"
Tuesday 29th November, 2022 12:00 – 13:30 GMT FREE to attend Online RISC-V Verification Strategies With the popularity of the RISC-V open architecture, many companies are looking for Verification Strategies …
Continue reading "DVClub Europe Meeting: RISC-V Verification Strategies"
* Company email is required* Register management tools have been used mostly in a bottom-up approach. There are some documents and/or spreadsheets created by the System Architects that are delivered to the design and verification teams. They then start capturing the HW/SW interface of the peripheral IPs in their in-house or commercial register management tool …
Continue reading "Webinar: Code Review for System Architects"
