Simulator performance is critical owing to the exponentially increasing complexity of SoC designs and shrinking market time. Cadence® Xcelium™ is a leader in simulation performance, and we focus relentlessly on improving the core performance of the simulator. We keep developing new performance optimizations that are delivered with each new release of Xcelium. It is easy to achieve …
Description Multi-die designs allow systems engineering to pack more functionality with different timing and power constraints into a single package. Older generation multi-die split the dies into high-speed and low speed. Newer, high-performance multi-die System-on-Chip (SoC) requires interaction between memories across the die-to-die interfaces. Connections between dies must be power efficient, have low latency, provide …
Continue reading "Webinar: Evaluating UCIe based multi-die SoC to meet timing and power"
A worldwide connected Event!! IP-SoC 2022 will be the 25th edition of the working conference fully dedicated to IP (Silicon Intellectual Property) and IP based electronic systems. The event is the annual opportunity for IP providers and IP consumers to share information about technology trends, innovative IP SoC products, Breaking IP/SoC News, Market evolution and more. …
* Company email is required* Register management tools have been used mostly in a bottom-up approach. There are some documents and/or spreadsheets created by the System Architects that are delivered to the design and verification teams. They then start capturing the HW/SW interface of the peripheral IPs in their in-house or commercial register management tool …
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*Company email required for registration* If you are designing chips for high-performance computing (HPC) and data center applications, bandwidth is, of course, a key consideration. However, as data centers get bigger and the required compute power increases, keeping power consumption to a minimum becomes a priority. In addition to power, latency is another key concern …
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D&R IP-SoC Silicon Valley 2023 Day is the unique worldwide Spring event fully dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems. IP-SoC providers, the seed of innovation in Electronic Industry, are invited to highlight their latest products and services and share their vision about the next innovation steps in the Electronic Industry. …
Performance Testing and Analysis Discuss the performance verification challenges posed by complex SoC with distributed cache from cluster, to interconnect to die-to-die. Agenda (BST) 12:00 Welcome and Introduction – Mike Bartley, Tessolve 12:00 Nick Heaton, Cadence Design Systems - SoC Verification in a Multi-chip, Multi-die world 12:30 David Kelf, Breker Verification Systems - Automated SoC Performance and …
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SoCs have become very complex silicon solutions. They now consist of 100s of millions or billions of gates, 100 or more discrete Semiconductor Intellectual Property (SIP) blocks, megabytes of volatile and non-volatile embedded memory and multiple CPU cores. Join us on Thursday, April 27 for this 30-minute webinar as we describe and quantify the benefits …
Continue reading "Webinar: How Deep Data Analytics Accelerates SoC Time-to-Market by 6 Months"
Wednesday, June 14, 2023 | 10:00 a.m. - 11:00 a.m. CEST Verifying an SoC is an extremely complex process that requires agile turnaround, constant control feedback, and flexibility to adapt to evolving project needs. Coverage is an efficient metric for the number of potential bugs found and needs to be tracked at each stage of …
Overview CadenceCONNECT Singapore Technology Seminar 2023 will introduce you to optimized design methodologies for electronics system applications. The event brings together Cadence technology users, developers, and industry experts for networking, sharing best practices on critical design and verification issues and discovering new techniques for designing advanced silicon, SoCs, and systems. Date: July 10 (Monday) Time: …
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*Company Email is Required for Registration* This webinar explores front-end automation advances that encompass an innovative register information management system to capture hardware functionality and addressable register map in a single "executable" specification. Appropriate Audience: ● Architects/RTL Designers ● Verification Engineers ● Pre-Silicon Validation Teams ● Post-Silicon Lab Bring-up Team Members ● Technical Writers ● …
Chiplet-based SoC architectures have seen increased interest over the past three years, and recently were made a focus of the federal CHIPS and Science Act to reduce the cost of innovation for US-based semiconductor startups, DoD projects, and academic research. Chiplet-based architectures bring their own set of challenges however, especially in the context of IP …
Continue reading "Webinar: IP Lifecycle Management for Chiplet-Based SoCs"
