Solido Lunch and Learn Seminar: Variation-Aware Verification and Library Characterization Powered by Machine Learning

Fremont, CA Fremont, CA, United States

Overview The ever-demanding and expanding applications in automotive, high-performance computing, mobile, and IoT are the driving force behind the increasing complexity of today’s semiconductor designs. Because of this, design and verification methodologies that were “good enough” in the past, are no longer adequate to service the requirements and meet specifications. Most existing methodologies fall short …

Seminar: Low Power Verification Forum

El Segundo, CA El Segundo, CA

Overview Reducing power consumption is a mainstream and essential design requirement for many industry segments; including networking, milaero, mobile, automotive, consumer, IoT and many others. Besides using power management techniques, design teams are also trying to reduce their power in the RTL design process by reducing unnecessary switching activity. This process can be difficult and …

Seminar: Mentor Forum for Tessent DFT 2019 India

Radisson Blue, Bengaluru Bengaluru, India

Overview Test for the Autonomous Age The seminar will focus on three key test challenges IC vendors face as they try to make the promises of the autonomous age a reality. Implementing DFT on the very large designs and new compute architectures that are required for efficient AI and machine learning Achieving high test quality …

Seminar: 2.5D/3D IC Packaging Verification

Fremont, CA Fremont, CA, United States

Overview Do you want to find out, hands-on, how many of the leading fabless semiconductor companies are verifying their complex 2.5/3D heterogeneous and homogeneous package assemblies?  Here is your chance to meet our technical staff and ask your questions.  Come and see why fabless semiconductor companies are adopting this flow, irrespective of the Package layout …

Seminar: 2.5D/3D IC Packaging Verification

Fremont, CA Fremont, CA, United States

Overview Do you want to find out, hands-on, how many of the leading fabless semiconductor companies are verifying their complex 2.5/3D heterogeneous and homogeneous package assemblies?  Here is your chance to meet our technical staff and ask your questions.  Come and see why fabless semiconductor companies are adopting this flow, irrespective of the Package layout …