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Seminar: Mentor Forum for Tessent DFT 2019 India
September 17 @ 9:00 am - 5:00 pm
Test for the Autonomous Age
The seminar will focus on three key test challenges IC vendors face as they try to make the promises of the autonomous age a reality.
- Implementing DFT on the very large designs and new compute architectures that are required for efficient AI and machine learning
- Achieving high test quality and fast yield ramps with the advanced process technologies incorporating 3D transistors
- Meeting the requirements of a growing number of autonomous market segments like automotive that have functional safety requirements
- Efficiency of run-time
- Some road map focus
- New Trips and Tricks
What You Will Learn
- Artificial Intelligence (AI) and other leading edge technologies are experiencing explosive growth in both the number of SoC designs as well as increased complexity. AI processors have architectural features and physical design practices that challenge all aspects of design including DFT. We will investigate some of the DFT challenges faced by AI designs and look at approaches that are currently being used. A few published methodologies and results will be reviewed.
- The defection of defective devices during production test continues to become more demanding as automotive devices strive for single digit to zero defects per billion quality levels. Increasing needs for better test quality exist in many other industries where devices are more complex and expensive. Detecting defective devices during IC test has a significant impact on profitability and help avoid costly high level and system level tests. This talk will show the latest test quality methods employed in Automotive-grade ATPG and analog fault simulation for fault grading and pattern set effectiveness measures. We will demonstrate industry results for both methods.
- EDA companies used to supply discrete DFT tools for ATPG, or memory BIST, or other functions. Semiconductor DFT teams has traditionally been developed with the overall device in mind and were responsible for the SoC level integration. This is no longer possible. DFT for modern SoCs requires methodologies to address design scaling with plug-and-play principles and automation. The Tessent platform was developed over many years to solve these issues by providing one common tool and common database which includes various DFT functions such as ATPG or BIST as well as top level and hierarchical integration. As a result, users can achieve demanding schedule with automation and hierarchical/SoC level integration. The DFT methodologies described here are designed to address continued design scaling with plug-and-play principles and automation.
Who Should Attend
- All DFT test and product engineers and management who are interested in high quality at lowest test cost. Understanding emerging technologies in Design for Test to enhance quality simultaneously managing cost.
- Design Engineers
- Test Engineers
- CAD Engineers & Managers