Seminar: Low Power Verification Forum

Overview

Reducing power consumption is a mainstream and essential design requirement for many industry segments; including networking, milaero, mobile, automotive, consumer, IoT and many others. Besides using power management techniques, design teams are also trying to reduce their power in the RTL design process by reducing unnecessary switching activity. This process can be difficult and the ultimate effect from RTL modifications are hard to predict. This forum will explore the new and unique low power coverage methodologies that enable designers to verify and track how well they have tested their power management architecture. It will also show how to track not only metrics for how much power is used in the RTL, but also how much power is still being wasted and has potential to be reduced for IP qualification. Finally, it will step through how to bring real power scenarios into both your power measurement and management coverage metrics to provide the final phase of power verification and analysis.

Who Should Attend

Design and Verification Engineers and Managers

Products Covered

• Questa® Power Aware Simulator