Register For This Web Seminar Online - Jun 29, 2020 9:00 AM - 10:00 AM US/Pacific Register Online - Jun 29, 2020 5:00 PM - 6:00 PM US/Pacific Register Overview Mentor will highlight our Tanner Digital Implementer (TDI) tool, powered by the Oasys Digital Synthesis and Nitro Place and Route engines, and its integration into …
Continue reading "Complete RTL to GDSII Flow for “Analog on Top” Designs"
Register For This Web Seminar Online - Jun 29, 2020 9:00 AM - 10:00 AM US/Pacific Register Online - Jun 29, 2020 5:00 PM - 6:00 PM US/Pacific Register Overview Mentor will highlight our Tanner Digital Implementer (TDI) tool, powered by the Oasys Digital Synthesis and Nitro Place and Route engines, and its integration into …
Continue reading "Complete RTL to GDSII Flow for “Analog on Top” Designs"
The hardware/software interface, or HSI is the critical piece of technology that allows software to communicate with the hardware it’s controlling. With all the dedicated processors in most designs today, this is a very important part of the architecture. If it doesn’t work, the product doesn’t ship. If it has a subtle bug, new features …
Continue reading "Three Perspectives on the Hardware/Software Interface – Who’s Right?"
08 Mar 2022 Online Event Details Want to take a tour of this powerful power estimation tool and gear up so you understand the Joules flow? Join Cadence Training and Sr Principal Education Application Engineer Neha Joshi for this free technical Training Webinar. Built on a multi-threaded frame-based architecture, the Cadence® Joules™ RTL Power Solution delivers 20X faster time-based RTL …
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Date: Thursday, September 22, 2022 Time: 12:00pm - 1:00pm (PDT) As semiconductor process technology advances, predicting and achieving design power, performance, and area (PPA) goals become increasingly difficult. Developing high-performance algorithms for AI and signal processing is particularly challenging as algorithm development is abstracted from design implementation, often resulting in late discovery of performance issues. …
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*Company email required for registration* Register Transfer Level (RTL) power analysis, performed early in the design cycle, is a key component of end-to-end methodology to maximize energy efficiency. Such analysis has become a critical requirement for many IC designs today and in the future. Although RTL power analysis technology has been available to designers for …
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As designs get increasingly complex, design teams are looking to find bugs earlier, to reduce rework and shorten time-to-market. The ultimate “shift left” is to put easy-to-use static verification in the hands of RTL designers to eliminate bugs at their source. This webinar covers comprehensive static verification capabilities in the Cadence® Jasper™ Superlint and CDC apps for …
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Synopsys Webinar | Thursday, July 20, 2023 | 10:00 a.m. - 11:00 a.m. Pacific As today’s designs are getting more complex, design constraints complexity also increases multifold. While ensuring design correctness typically gets a lot of attention including code review, functional verification, implementation, etc., correctness of constraints requires the same level of attention. Quality of …
Wednesday, July 26, 2023 | 10:00 a.m. - 11:00 a.m. PDT RTL engineering change order (ECO) is vital to ensuring proper functionality of integrated circuits (ICs). Retiming and auto ungrouping optimize RTL implementation and enhance PPA. However, aggressive optimizations in CPU RTL designs present challenges due to increased design complexity and potential mapping issues. Synopsys Formality …
Accelerate Coverage Closure with VSO.ai Virtual Workshop - North America Wednesday, September 27th, 2023 | 9:00 a.m. - 1:00 p.m. PT Virtual workshop with hands-on labs Achieving coverage closure continues to remain a challenge for customers and there is a growing need for a system to work autonomously to reach the target as quickly and cheaply …
Designers face enormous challenges for low-power designs. Whether it is IoT at the edge, AI in the datacenter, robotics or ADAS, the demand for increased functionality in SoCs is rapidly outpacing the power budget. Power must be considered at every stage of chip design including performance, reliability and packaging. Waiting to address power until late …
Would you like to know how to design a complete chip using the RTL-to-GDSII Flow? In this free technical Training Webinar with Application Engineer Sai Srinivas Pamula, we’ll teach you the essential steps in the RTL-to-GDSII design flow using a wide variety of industry-leading Cadence tools—such as the Xcelium Logic Simulator, Modus DFT Software Solution, …
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