Abstract: The Open Component Portability Infrastructure (OpenCPI) is an open source software (OSS) framework for developing and executing component-based applications on heterogeneous systems. By targeting heterogeneous systems, the framework supports …
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Sunil Sahoo, Corporate Applications Engineer Thursday, October 20, 2022 11:00 AM - 12:00 PM (PDT) Abstract: Coverage is an essential part of any verification environment. Coverage can be simple as a statement and branch coverage, or it can be more complex as a covergroup with constrained-random tests. Implementation, collection and analysis of coverage on your …
Continue reading "LIVE WEBINAR: Optimizing Simulations for Efficient Coverage Collection (US)"
Philipp Wagner, Co-maintainer of cocotb and Hardware/Software Engineer at lowRISC Abstract: Writing code is easy. Reading code is hard. Maintaining code is hard. Writing "good" code is hard. So what's "good code"? Don't despair: the software engineering community has come up with tons of practical solutions! Now it's time to apply them to your next …
Summary The use of advanced verification tools can significantly reduce the number of non-trivial bugs, save engineering time and resources and, more importantly, increase the reliability of FPGA designs. Static design verification is an essential part of a robust verification process that includes advanced linting and Clock Domain Crossing (CDC) analysis. In this webinar, we …
Continue reading "Webinar: Linting and Clock Domain Crossing Analysis for Microchip FPGA Designs"
Abstract The programming interfaces of logic simulators are largely the domain of specialists writing proprietary tools and extensions and are only vaguely in the consciousness of many design and verification engineers, if aware at all. Yet the simplest use of such interfaces opens up a whole world of possibilities in extending what is achievable in …
Continue reading "Webinar: The Power of Verilog’s PLI and VPI for FPGA Designs"
Abstract: Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series we will present a step-by-step approach on how to architect a testbench - progressing from basic to advanced techniques. We will first use a simple DUT then go to a more …
Abstract: Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series, we will present a step-by-step approach on how to architect a testbench - progressing from basic to advanced techniques. We will first use a simple DUT then go to a more …
Abstract: Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series, we will present a step-by-step approach on how to architect a testbench – progressing from basic to advanced techniques. We will first use a simple DUT then go to a more …
Time: 11:00 AM - 12:00 PM (PDT) Abstract As FPGA technology continues to evolve - to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the …
Time: 11:00 AM - 12:00 PM (PDT) Abstract As FPGA technology continues to evolve - to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area - design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient, especially for safety-critical designs, and FPGA …
Time: 11:00 AM - 12:00 PM (PDT) Abstract As FPGA technology continues to evolve - to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area - design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient, especially for safety-critical designs, and FPGA …
LIVE WEBINAR: Ways to run cocotb: makefiles, cocotb-test, or your custom setup (US) Philipp Wagner, cocotb and Hardware/Software Engineer at lowRISC Thursday, November 9, 2023 11:00 AM - 12:00 PM (PST) Abstract: cocotb enables Python-based hardware verification, and it integrates into your simulator of choice, such as Aldec's Riviera-PRO and executes Python testbenches in that context. …
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LIVE WEBINAR: System Simulation of Versal ACAP Designs (US) Louie De Luna, Director of Marketing, Aldec Thursday, November 16, 2023 11:00 AM - 12:00 PM (PST) Abstract: AVersal ACAP, developed by Xilinx/AMD, is a groundbreaking adaptable platform composed of AI Engine (AIE), Processing System (PS), Programmable Logic (PL), Network on Chip (NoC) and a wide range …
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