Time: 11:00 AM – 12:00 PM (PT) Abstract: Riviera-PRO™ Advanced Verification Platform addresses the verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, …
Time: 3:00 PM – 4:00 PM (CET) Abstract: The ALINT-PRO Static Design Verification solution includes DO-254 HDL Ruleset targeted for safety critical designs that require DO-254 compliance. Recently, this DO-254 Ruleset was enhanced with more than 80 new rules, adding a significant amount of code checks for Verilog and VHDL-based designs relevant to coding practices, clock …
Course Synopsis: Designed to provide a comprehensive understanding of DO-254 specification, objectives and requirements for airborne electronic hardware development, and teach efficient, well-proven and compliant methods to enable a faster, easier and more cost-effective path to FAA certification. Day 1: Understand the regulatory background for DO-254. Understand the guidance material for PLD development. Learn the …
Abstract: Designing FPGAs that use a single clock domain is a luxury that very few of us have. Modern FPGA designs must cope with multiple clocks running at different frequencies, very often asynchronous to each other, and still be expected to work reliably. Xilinx Parameterized Macros (XPM) can be used to implement CDC, FIFO and …
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Abstract: The FPGA design architecture is the single most important and primary factor in achieving development efficiency, quality and reliability. The difference between a good and a bad design architecture can be about 50% of the workload and a high degree of detected and undetected bugs. Most design architectures can be improved and optimized to …
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Part 2: FPGA Verification Architecture Optimization with UVVM (US) Espen Tallaksen, CEO of EmLogic Thursday, May 5, 2022 11:00 AM - 12:00 PM (PDT) REGISTER HERE Abstract: For most FPGA projects, over 50% of the overall project time is spent on verification. This time can be significantly reduced if the verification architecture is well-structured and …
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FPGA Design/Verification Best-Practices for Quality and Efficiency Part 3: Randomization – The Why, When, What & How (US) Time: 11:00 AM - 12:00 PM PDT Abstract: Randomization is very important for modern verification. Still, very few designers apply randomization sufficiently in their testbenches. This means they are missing out on a very important method for finding potential …
Espen Tallaksen, CEO of EmLogic Thursday, May 19, 2022 11:00 AM - 12:00 PM (PDT) Abstract: Functional coverage is often mentioned together with constrained-random verification, and this is a great combination. However, functional coverage is also very useful even if you have no randomization at all. This is a great method for ensuring that you …
Part 1: OSVVM - Leading Edge Verification for the VHDL Community (US) Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, and IEEE VHDL Chair Thursday, May 26, 2022 11:00 AM - 12:00 PM (PDT) Abstract: OSVVM is an advanced verification methodology that defines a VHDL verification framework, verification utility library, verification component library, …
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LIVE WEBINAR: Better FPGA Verification with VHDL (Four Part Webinar Series) Part 2: Faster than "Lite" Verification Component Development with OSVVM (US) Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, and IEEE VHDL Chair Thursday, June 9, 2022 11:00 AM - 12:00 PM (PDT) Abstract: Some methodologies (or frameworks) are so complex that …
Abstract: OSVVM has grown tremendously over the last couple of years. This period saw simulator independent scripting, test reporting, model independent transactions, virtual transaction interfaces, and additional verification components, each added and incrementally improved. We have talked about these previously in this webinar series. This webinar focuses on advances in OSVVM data structures. OSVVM's Functional …
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Abstract: The Open Component Portability Infrastructure (OpenCPI) is an open source software (OSS) framework for developing and executing component-based applications on heterogeneous systems. By targeting heterogeneous systems, the framework supports development and execution across diverse processing technologies including GPPs (general purpose processors), FPGA (field programmable gate arrays), and GPUs (graphics processing units) assembled into mixed …
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