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LIVE WEBINAR: FPGA Design/Verification Best-Practices for Quality and Efficiency
The FPGA design architecture is the single most important and primary factor in achieving development efficiency, quality and reliability. The difference between a good and a bad design architecture can be about 50% of the workload and a high degree of detected and undetected bugs. Most design architectures can be improved and optimized to increase both quality and efficiency.
- State of the FPGA community
- Examples of bad FPGA design architectures (results and disadvantages)
- How to improve and optimize FPGA design architectures (results and advantages)
- How design and design changes can be simplified
- Questions and Answers
- 45 min presentation/live demo
- 15 min Q&A
Espen Tallaksen, CEO of EmLogic
Espen is also the author and architect of UVVM and founder of previous Bitvis.
He has a strong interest in methodology cultivation and pragmatic efficiency and quality improvement, and he has given many presentations at various international conferences with great feedback. He has also given courses on FPGA Design and Verification in three different continents.