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STMicroelectronics is designing complex SoCs in advanced technology nodes, containing tens of thousands of embedded memories. Many divisions at STMicroelectronics chose to use the Synopsys Star Memory System (SMS) IP for test, repair and bitmap of their most advanced products. This presentation describes the flow setup by STMicroelectronics R&D and Networking divisions to test and …
Ever looked at the complexity of duplicating your EDA workflows to run in the cloud? Is your CFO worried about running up huge bills for using the cloud? Want to just be up and running in the cloud? The answer? IC Manage Holodeck AWS Marketplace Edition IC Manage Holodeck AWS Marketplace edition can get you …
Traditional coverage-based verification methods are no longer sufficient to verify complex SoCs integrating many processor cores and IP subsystems. To conquer the verification challenge of complex SoCs, companies are shifting their development paradigm to a software first approach. By considering the target software up front, as a critical part of the SoC development process, designs …
The hardware/software interface, or HSI is the critical piece of technology that allows software to communicate with the hardware it’s controlling. With all the dedicated processors in most designs today, this is a very important part of the architecture. If it doesn’t work, the product doesn’t ship. If it has a subtle bug, new features …
At Veriest, we believe in knowledge sharing. In our recent meetup events, hundreds of professionals from 20+ different countries gathered to listen to different industry experts from companies such as Intel, ST Microelectronics, arm, Texas Instruments, Nvidia and more. This time, we'll focus on the polemic topic of using Python in Verification. We'll have two presentations, both …
Wednesday, March 9, 2022 | 10-10:45 a.m. PST Complex bus protocols, increased on-chip functionalities, coupled with limited shared I/O resources, result in complex wiring connections in SoCs with numerous muxing schemes. Simulation and structural analysis approaches require huge effort and may lead to bug escapes making them inefficient for SoC connectivity verification. Connectivity verification using …
• Do you need to estimate the power advantage of implementing an AI algorithm on an accelerator? • Do you need to size the AI accelerator for existing and future AI requirements? • Would it be beneficial if you knew the latency advantage between ARM, RISC, DSP and Accelerator in deploying AI tasks? This webinar …
About this talk In specifying the features, functions, and requirements of a main processor and AI accelerator (NPU), system engineers and chip architects often don't consider use cases. In this webinar, Expedera VP of Marketing Paul Karazuba and Andes Technology Director of Field Applications John Min will examine typical use cases system designers face, and …
Date / Time: Thursday, March 31, 2022, 11:00 a.m. New York / 4:00 p.m. London Overview: sponsored by Especially inside the large data centers that underpin today’s cloud and internet infrastructure, traffic keeps growing exponentially. As a result, the industry is now looking at 800G- and even 1.6T-capable optical (pluggable) transceivers, and co-packaged optics with even …
Advanced semiconductor nanometer technology nodes, together with smart IC design applications enable today very complex and powerful systems for communication, automotive, data transmission, AI, IoT, medical, industry, energy harvesting, and many more. However, more aggressive time-to-market and higher performance requirements force IC designers to look for advanced and seamless design flows, tools & methodologies to …
Thursday, May 12, 2022 | 10:00 - 11:00 a.m. Pacific During complex IP development, effort and time taken to perform a functional ECO is very high. It involves analysis and understanding of huge combinational and sequential blocks, and usually runs into multiple iterations if done manually. For example: the physical netlist multibit register mapping could …
