Balancing Performance and Power in adding AI Accelerators to System-on-Chip (SoC)

• Do you need to estimate the power advantage of implementing an AI algorithm on an accelerator?

• Do you need to size the AI accelerator for existing and future AI requirements?

• Would it be beneficial if you knew the latency advantage between ARM, RISC, DSP and Accelerator in deploying AI tasks?

This webinar focuses on design teams transitioning to an AI accelerator in their next-generation SoC processor. In the webinar, we will use VisualSim system-level modeling and hardware-software partitioning technology in migrating an algorithm to an AI accelerator.

The SoC architecture will be tested for a variety of workloads and use-cases. The new VisualSim Insight methodology will be deployed to track the requirements through SoC planning, design, validation and testing. The generated diagnostics and metrics will be used to make decisions on the right AI accelerator configuration.

AI accelerators can be built with a variety of configurations- single vs. multi-core, 2 or 3 level caches, Network-on-Chip (NoC) vs. AMBA AXI bus, or LPDDR vs. DDR5. At the same time, the task partitioning can be based on lowest power, latency, memory throughput, or smallest size of each IP block.

Join this webinar to understand the power, sizing and latency advantages obtained through AI Accelerators.

Speaker: Tom Jose is a Research & Development Engineer at Mirabilis Design. A System Design Architect & Trainer, he supports companies and universities to build their own design. He has published three papers – RISC-V & ARM processor comparison at the RISC-V international conference, Using AI for optimal Time Sensitive Networking in Avionics & Functional Safety for Braking System through ISO 26262, and Operating System Security and DO 254. He has worked with the micro architecture design of processor pipeline stages, instruction implementation, verification and workload partitioning. This webinar is in partnership with SemiWiki and Mirabilis Design.