Loading Events

« All Events

  • This event has passed.

Mentor Forum for Verification 2019 India

August 28

Register For This Seminar

Bangalore – Aug 28, 2019 
8:45 – 17:30 IST

Hyderabad – Aug 30, 2019 
8:45 – 17:30 IST

Overview

Our industry has experienced remarkable breakthroughs in automotive, networking, and communication technology in recent years. Yet, it is the convergence of these technologies that is driving the next big thing in innovation related to IoT and autonomous systems. In addition, it is also driving the need for new approaches to verify today’s complex systems.

Today’s complex designs rely heavily on a growing variety of complex industry standard interfaces that must be verified to ensure IP interoperability and system behavior. Mentor’s verification IP (VIP) improves quality and reduces schedule times by building Mentor’s protocol and methodology expertise into a library of reusable components that support many industry standard interfaces. This frees up engineering resources from having to spend time developing BFMs, verification components, or VIP themselves, enabling them to focus on the unique and high-value aspects of their design.

Functional Safety is becoming super critical with the growth in the automotive sector. Because of the risks involved these industries have put in place strict rules for requirements tracking and testing to ensure the mission does not fail. Many application even required that an outside auditor review the project to ensure compliance with these rules.

Use of Static and Formal tools to complement design verification using dynamic simulations have come a long way. The industry has made it easier to use and debug formal solutions.

This event will address a varied set of challenges in the world of IP/SubSystem/SoC design and verification and also look at how we can address some of these challenges.

What You Will Learn

  • Latest industry trends in Verification across the world
  • Overview of Coverage Closure techniques using Portable Stimulus
  • Functional Safety Flow
  • Usage and debug of various Verification IPs
  • Challenges in Clock Domain Crossings and how to address them.
  • Doing effective Formal verification?

Who Should Attend

  • ASIC/IC/SoC/FPGA Design & Verification Engineers
  • Project Leads
  • Managers
  • Design Engineers
  • CAD Managers

Agenda

08:45 AM-09:30 AM   Registration
09:30 AM-09:40 AM   Welcome
09:40 AM-10:10 AM   Mentor Keynote
10:10 AM-10:40 AM   Industry Keynote
10:40 AM-11:00 AM   Coffee/Tea Break
11:00 AM-11:45 AM   Mentor Enterprise Verification Platform
11:45 AM-12:30 PM   Functional Coverage Closure with inFact + Testimonial
12:30 PM-01:45 PM   Lunch
01:45 PM-02:30 PM   Formal Verification made Easy + Testimonial
02:30 PM-03:15 PM   Addressing Clock Domain Crossing Challenges with Questa CDC
03:15 PM-03:30 PM   Coffee/Tea Break
03:30 PM-04:15 PM   Verification IP
04:15 PM-05:00 PM   Functional Safety flow5:00 PM 5:30 PM   Wrap & Closin