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DVClub Europe – Cache Coherency Verification
September 5 @ 12:00 PM - 1:00 PM
Cache Coherency Verification
SoC cache coherency verification is one of the most complex challenges faced by verification engineers. And the introduction of the embedded L3 cache and the increasing number of cores in CPU clusters ais making it even more challenging. In this DVClub we will focus on how this challenge can be best approached and some automation added.
Agenda (BST)
12:00 Welcome and Introduction – Mike Bartley, Senior Vice President – VLSI Design, Tessolve
12:00 David Kelf, Breker Verification Systems
12:20 Sponsor Speaker
12:40 Sponsor Speaker
13:00 Close
About DVClub
The principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe meetings is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences, insights and issues with other members of the verification community.
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