CadenceTECHTALK: Automated Verification for Cache Coherent RISC-V SoCs

Date: Tuesday, July 18, 2023

Time: 11:00 AM PDT | 1:00 PM CDT | 2:00 PM EDT

RISC-V SoC design complexity continues to increase and create new verification challenges. Private caches, shared caches, and shared main memory create potential caches/memory coherency problems that require modern, automated verification approaches.

In this webinar, we’ll demonstrate how Perspec System Verifier, with the pre-defined System Traffic Library (STL), provides an out-of-the-box verification plan and test suite for heterogeneous, multi-core, and cache-coherent processors. STL has built-in atomic actions and coherency scenarios to allow verification engineers to quickly generate test scenarios, such as targeting false sharing, true sharing, cache state transitions, snoop traffic, coherency irritators, extreme stress scenarios, IO coherency, and many more areas. Perspec System Verifier also helps visualize scenarios and analyze coverage before test execution.

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