WEBINAR: Design Adaptive eFPGA IP

Since the start of PROMS, PLDs and FPGAs we have learned the importance of programmability in modern semiconductor design. Today we have eFPGAs for “design adaptive” embedded programmability and that is what this webinar is all about.

Several key points are discussed starting with the Law of Accelerating Returns as it applies to integrated circuits followed by Semiconductor Trends, the Makimoto Wave, and Design Cycles & Rhythms of Change. This is a great overview for the young and old, absolutely.

We then dig into the nuts and bolts of FPGA, ASIC, SoC, Processors and  eFPGAs followed by the Menta Design Adaptive eFPGA IP and the benefits of programmable logic without the pain.

The speaker is Yoan Dupret, whom I met at the Design Automation Conference a few years back. Yohan is an innovator with a PhD and more than 15 years experience in the semiconductor industry including various management and technical positions in companies such as DelfMEMS, Samsung, CSR, Infineon and Altis Semiconductor prior to Menta.

In addition to his embedded FPGA expertise, Yoan worked on topics such as RF MEMS design, EDA, PDK, MOS and passives RF modeling, statistical simulation and manufacturing yield modeling.

As I have mentioned before, it is a privilege to work with so many incredibly intelligent people inside the semiconductor ecosystem and Yoan is one of those people, absolutely.

Register HERE for the replay.

Abstract:
Despite the current health crisis, we are living through an unprecedent era of innovation – and this is not going to slow down as well captured by the law of accelerating returns. Disruptive and rapid change is now the new constant. The rate of architectural and algorithmic innovation is outpacing traditional chip development cycles. This is not only true for AI, but also for communication protocols, encryption, compression, interconnect fabrics and cybersecurity. The old world order of computing has now fractured beyond recognition. Now is the time to design chips to be at least partially reconfigurable to adapt to emerging needs.

Embedded programmable logic, in the form of embedded FPGA (eFPGA) IP, is now making its way in SoCs as an answer to these challenges, with multiple design wins announced by the main eFPGA IP providers.

In this webinar, we will explain what makes an eFPGA different to a FPGA but also to embedded CPUs/GPUs – and in which cases an eFPGA IP is the way to go. We will then explain what is a design adaptive eFPGA IP and why this adaptiveness is so important when it comes to integrating an eFPGA IP.

Here are the questions I have for the Q&A. Send me your questions and I will make sure they are answered:

• If I have RTL working on an off the shelf FPGA, how hard is it to port it to a Menta eFPGA IP?
• You mention foundries, do you work with IDMs as well?
• What kind of applications are run by your customers?
• Is there a way to secure the bitstream?
• Any export limitations?
• What percentage of the chip is usually taken by the eFPGA?

Register HERE for the replay.

About Menta
Menta is a privately held company founded in 2007 in France. The company delivers 100% third party standard-cells embedded FPGA IPs for SoC, ASIC or ASSP designs. Our technology lets you effortlessly update your silicon post-production, whether to fix a bug, implement customer-specific features, adapt to evolving standards, or enhance security.  Menta IPs are delivered with the Origami toolchain to generate the bitstream from RTL, including synthesis. Menta is backed by FJ Development EN, with an investment of more than $7M to date.