Last year at DAC we didn’t really know the circuit simulation roadmap for Synopsys because of all the EDA company acquisitions, however this year it’s clear to me that:
- HSPICE continues on, although it’s a lower performance circuit simulator than FineSim
- FineSim from Magma is well-loved, and faster than HSPICE
- HSIM kind of disappeared this year in favor of CustomSim instead
- AMS simulation using VCS and HSPICE/CustomSim works
- There’s plenty of circuit simulator and AMS competition from: Berkeley DA, Cadence, Mentor and the smaller vendors
- Synopsys has a new tagline, “Accelerating Innovation”, but I don’t remember what the previous tagline was
Synopsys had five customers talk about their actual AMS design and simulation experiences, which was more interesting than having product marketing speak.
Farhad Hayat (Synopsys)
Fuad Bardieh (Micron), George Lattimore (ARM), Sebastien Cliquennois (ST-Ericsson), Jaynie Shorb (Broadcom), Florian Cacho (STMicroelectronics)
Fuad Badrieh, Micron
On-chip and off chip power delivery modeling with HSPICE. Principal engineer.
Impedance optimization across frequency.
– High chip currents stress the PDN, higher clock rates with inductance creates voltage issues, using de-coupling capacitors.
– overview of the Power Delivery Network with on-chip die model for DRAM modules like DDR3, DDR4, etc. Voltage regulator used for a multi-layer PCB. Modeling the entire VCC from regulator to PCB to component, to package, to the circuit. Model the PDN as a schematic, then do layout and extract the SPF with actual parasitics. How much VCC is lost going from the regulator to the transistors in the memory? Created a 3D plot of VCC loss across the system, shows good correlation between schematic and actual in both DC and AC modes. Can replace the entire system with an equivalent RC model.
– Used both HSPICE and FineSim to simulate currents and voltages across the entire PDN. Analysis allows optimization to take place and VCC optimization.
– All the impedances are frequency dependent for Board, Package and Chip. Adding decoupling capacitances manages effects of VCC loss. Resonance can be minimized. ESR effects on resonance can be simulated then optimized.
– current demands with spectral analysis.
– Multiport elements are simulated in HSPICE
– FineSim can simulate large grids with 1.2M AC elements (Resistors, Caps) in under 1 minute.
George Lattimore, ARM
FinFET memory IP design with FineSim.
Director of Engineering for Physical IP division, in Austin they do both std cell and memory compilers and IO.
– Used FineSim to simulate these compilers. Samsung, TSMC, GF and IBM all have FinFET processes.
– Lower VDD levels, FinFET width quantized, memory power-gating.
– Memory compilers have single and multi-bank design architectures, so customers can trade-off PPA.
– Lots of RAM required to simulate in FineSim these SPICE netlists. Some compilers need 4GB of RAM, others take 26GB of RAM to simulate.
– FinFET netlists are 3-5x larger because of parasitic RC elements. About 3-10X runtime increase because of modeling. 2-3X increase in RAM to simulate a circuit.
– FineSim uses a Table model to reduce RAM and runtimes, about 7.2 to 2.0X speedup.
– PowerBlock detection in FineSim to improve run time and reduce RAM requirements.
– Over the past 5 quarters FineSIM was used on 20nm designs and the average runtime has improved 45%.
– RAM usage improved 25 to 35% improvement.
– Accuracy compared to SPICE within 3%.
Improvements confirmed with both 14nm and 20nm nodes.
– Run times went from 3 days to 1/3 day over a 5 quarter period.
14nm simulation runs about as fast as 20nm netlists using FineSim improvements. 14nm is alpha-level models right now, no full IC layout yet.
-Foundry has improved models to run better with FineSim, collaborate with Foundry, FineSim, ARM.
Sebastien Cliquennois, ST-Ericsson
AMS CAD group.
Verification of an AMS design using SPICE on top, a power management IC.
– Using VCS
– Dynamic Analog IPs using VHDL, digital core with VHLD/Verilog, static analog IP with SPICE, application components in SPICE, testbench in VHDL with real numbers (functional test vectors, assertions).
– SOme ports are real number ports to control the analog behavior required.
– One test bench used for both digital and SPICE on top flows.
– Verifies the connectivity of the entire design.
– Can model in VDL with real numbers for intensive blocks like a switched DC DC converter, compared to SPICE.
– Goal: auotmatic verification after design changes in AMS design. Use of assertions for design verification.
– Verifying a full circuit in SPICE takes too much time. A PMU test cases with 5 million devices. 1 core would take 27 days in SPICE. Used a 12 core CPU and simulation went down to 9 days (acceptable). Replace the DC DC converters with VHDL models, now simulation in VCS taking just 1 hour.
– Lessons learned: Use IP models in VHDL with real numbers. Use Testbenches in VHDL with real numbers. Use multi-core CustomSim-VCS.
Full SPICE startup simulation in 10 days, never possible before. Uncovered 5 bugs with this new methodology, saving us time and money. First silicon success..
Jaynie Shorb, Broadcom
Principal Design Engineer.
memory characterization flow using FineSim. The design CAM as a compiler.
They design std cell, memory and IO cells.
CAM memory compiler was developed at Broadcom, uses a simple GUI for users to create what they need in hours or days. 128 bits to 2Mbits, 2 to 256 bits per word. The GUI has a web interface, then estimates PPA metrics within 20% of final result.
– Memory layout created in Skill code.
– the parastics are extracted with Star RCXT. OA is the database.
– This large extracted netlist gets reduced, then simulated in FineSim, SPICE mode. The timing and power numbers go into model generation.
– Lots of SPICE simulations to create the compiler, both FineSim Pro mode simulation, and Monte Carlo.
– Post layout simulations used for characterization with a reduced RC netlist,simulate with FineSim Pro.
– SImulations done for both dynamic and leakage power using FineSim Spice mode.
– Have to simulate all of the modes: standby, split rail, pwer down.
models generated for: Prime Time (SDF files), back-annotated to Verilog.
FineSim Pro runs the entire memory netlist, runs in minutes to hours based on size and parasitics. Pro is accurate enough compared to full SPICE. Mostly use FineSim Pro MD and FineSIm Spice MD.
Florian Cacho, STMicroelectronics
Aging Model implementation using MOS reliability API from HSPICE to CustomSim.
– So sorry, had a 1:00PM appointment and this luncheon was running long on time, so I had to miss this customer presentation.
Synopsys has plenty of circuit simulator products and at least we know which ones are alive and dead in 2013. It would make sense to me if HSPICE and FineSim merged together sometime in the future because they have much feature overlap. The need for speed without losing accuracy is a never-ending competition with circuit simulators and Synopsys looks to be holding their own, for the moment.