A Better Way for Analog Designers to Perform Variation Analysis

The impact of process variation at advanced nodes is increasing — no surprise there. In recent years, the principal design emphasis to better reflect this variation has been the adoption of two new methodologies: (1) advanced on-chip variation (AOCV, as well as POCV/LVF) for digital static timing analysis, and (2) advanced statistical analysis and Monte Carlo methods, including high-sigma Monte Carlo analysis.

High-sigma Monte Carlo has been adopted for applications where circuit performance and reliability requirements necessitate results beyond a traditional 3-sigma yield. Although high-sigma Monte Carlo methods are most often used in memory array analysis, a growing proportion of analog designers are also using high-sigma Monte Carlo verification to meet their customers’ performance and yield requirements. Whereas memory circuits require 6-sigma analysis to estimate the failure rate and confirm a suitable yield for the vast number of bitcells integrated on-die, analog designs require 6-sigma analysis to achieve the extreme reliability and yield requirements necessary for products upon which human life depends or where extreme environmental conditions are present — such as medical and automotive applications.

The team at Solido Design Automation has focused on optimization of Monte Carlo methodologies, with sophisticated algorithms to provide process variation analysis results that are both accurate and efficient. Their parameter sampling approaches cover two regions: (1) the 3-sigma region, where historically analog designers have concentrated the majority of their statistical simulation efforts, and (2) the high-sigma region, which has become more accessible to designers of all types in recent years due to advanced technology like Solido’s High-Sigma Monte Carlo. Solido’s high-sigma approach minimizes the number of Monte Carlo circuit simulations required to provide extreme statistical distribution data, which having specific testcase parameter detail for design exploration and optimization.

I recently spoke with members of the Solido team about features in the latest Version 4 release of Variation Designer. For memory designers, one of the key enhancements in this release is the Hierarchical Monte Carlo support for high-sigma array analysis — a brief summary of that discussion is available here.

Then, the Solido team discussed another new feature in Variation Designer — Statistical PVT.

They highlighted, “Digital library IP designers are used to dealing with process variation in terms of a fast/slow global corner, at best-case/worst-case voltage and temperature conditions. The (correlated) local variation around that global definition is used to verify setup/hold timing checks and array yield. Yet, that method won’t suffice for analog IP designers, whose designs can’t reliably be bounded by fixed fast/slow corners. What is a ‘fast’ gain, or a ‘slow’ bandwidth? Analog designers need design-specific, technology-specific, measurement-specific corners that correctly capture the bounds of their circuit specifications.”

Solido’s Variation Designer now offers Statistical PVT, in which fixed digital corners are supplanted by accurate analog statistical corners. Unlike the traditional approach of simulating combinations of fixed process, voltage, and temperature conditions and then also running Monte Carlo simulation, Statistical PVT combines Monte Carlo and PVT simulation to extract design-specific statistical corners and verify those across voltage, temperature, and other environmental conditions. This results in a more accurate and efficient analog variation analysis. (Actually, the “temperature inversion” characteristic of FET devices at advanced nodes increasingly impacts digital circuit performance, as well — Statistical PVT may not be solely of interest to analog designers.)

The figure below illustrates a setup screenshot from the application, which includes an extended sampling space for Spice simulations.

Analog IP typically incorporates a diverse set of additional on-chip components — e.g., R’s, C’s, diodes. In addition to applying variation to digital FF/SS MOS corners, Statistical PVT determines design-specific, technology-specific, and measurement-specific variation corners for the desired yield using variation models for each of these components. The following figure highlights how important it is to consider (passive) component variation, as well as device parameters. Considering only MOS devices fails to capture the possible variation present when other elements are included.

The sample sampling expertise used in the Solido HSMC methods is applied to an alternate method in Statistical PVT, to derive results representative of the 3-sigma performance with a reduced set of Monte Carlo simulations. For analog IP, the circuit simulation measurement specifications are vastly different than memory or cell library statistical characterization — e.g., gain, bandwidth, phase margin, duty cycle. The Solido team reminded me that their sampling optimization methodology is agnostic — “if you can measure it, we can analyze it” is their credo.

A key facet to statistical analysis is the evaluation and debug of post-simulation results.

The figure above illustrates the post-simulation user interface for a number of analog specification measurements. Note that the Solido results are not an extrapolation of a model or a brute-force exploration of the entire PVT space, but rather a specific set of simulation testcase parameters for the designer to examine in detail. Design optimization requires this testcase parameter detail, to help identify the circuit elements (and parasitics) to address. Although the description above uses an analog block for illustration, Statistical PVT is certainly applicable to RF circuits, too.

Key to analog IP design productivity is the Design History results view in Variation Designer, to provide the required perspective on the iterative optimization progress. The figure below illustrates the Design History user interface for a set of Statistical PVT runs and their corresponding revisions.

With an increasing breadth of application markets for advanced semiconductor processes — e.g., automotive, mil/aero, medical (and health-related IoT devices) — the SoC reliability requirements are demanding. Analog/RF IP validation requires a comparable simulation solution to High-Sigma Monte Carlo, as array and cell library designs have successfully applied. Solido’s Statistical PVT application within Variation Designer fits that need.

For more information on Statistical PVT in Variation Designer, please follow this link.

-chipguy

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