Solido and TSMC for 6-Sigma Memory Design

Solido Design Automation and TSMC recently published an article in EE Times describing how Solido’s High-Sigma Monte Carlo tool is used with TSMC PDK’s to achieve high-yield, high-performance memory design. This project has been a big part of my life for the past three years and it is time for a victory lap!

In TSMC 28nm, 20nm and smaller process nodes, achieving target yields is extremely challenging. Nowhere is this truer than for memory circuits, which aggressively adopt next bleeding-edge process nodes to help meet increasingly tighter performance specifications and higher levels of integration.

The article reviews the challenges raised by process variation, and in particular for memory with its high-sigma components. The article then discusses an approach to address variation with accurate statistical MOS modeling, plus the ability to analyze billions of Monte Carlo samples in minutes. This solution is now in place and rapidly gaining adoption.

The core reason for poor yield in memory is due to advanced process variations. The chips that roll out of manufacturing do not perform to the ideal, nominal simulated versions in design. If they do not meet parametric yield, they can’t be used. Process variation comes in many forms such as random dopant fluctuations, variations in gate oxide thickness, line edge and roughness. But their effect is the same: these random physical variations translate to variations in electrical device performances such as threshold voltage and transconductance. In turn, the device performance variations translate to variations in circuit performance such as power consumption, read current in a bitcell, or voltage offset in a sense amp. In turn, circuit performance variation means chip performance variation, causing yield loss.

The reason that variation is such an issue at 28nm and below is that the device sizes are getting within the same order of magnitude as the size of atoms themselves. We used to have Avogadro-size counts for the number of atoms in a device; but now those counts are in the thousands. The oxide layer on gates is down to just a few atoms thick, so even one or a few atoms out of place can cause performance variation of 20% to 50% or more.

The first case study in the article is a 6 transistor bitcell, using statistical device models from the TSMC 28nm PDK. With 6 devices, it has 60 local process variables. The second case in the article is a sense amp delay, having 15 devices and 150 process variables, also using statistical device models from the TSMC 28nm PDK.See the full articleHERE.

Also see:

EDA Tools to Optimize Memory Design, Size Standard Cells, Verify Low-Power Design, Center Analog Designs

TSMC Theater Presentation: Solido Design Automation!

Solido Design Automation Update 2012

High Yield and Performance – How to Assure?

A Survey of High-Sigma Monte Carlo Analysis Approaches

High-efficiency PVT and Monte Carlo analysis in the TSMC AMS Reference Flow for optimal yield in memory, analog and digital design!

Solido & TSMC Variation Webinar for Optimal Yield in Memory, Analog, Custom Digital Design

PVT and Statistical Design in Nanometer Process Geometries

Semiconductor Yield @ 28nm HKMG!

Solido – Variation Analysis and Design Software for Custom ICs

Variation Analysis

Variation-aware Design Survey

Moore’s Law and 28nm Yield