More Than Moore and Charting the Path Beyond 3nm

The incredible growth that the semiconductor industry has enjoyed over the last several decades is attributed to Moore’s Law. While no one argues that point, there is also industry wide acknowledgment that Moore’s Law started slowing down around the 7nm process node. While die-size reductions still scale, performance jumps and power reductions aren’t scaling as they used to. At the same time, die sizes for designs have been increasing at an unsustainable rate, reaching close to current reticle size limit. This has introduced a myriad of issues to tackle. The industry as a whole has been working on various ways to overcome the hurdles. A lot has been written up about various solutions being pursued to address specific aspects.

Something that I haven’t often come across is a treatise of Moore’s Law era and what is needed for the next era. One such presentation was made at the recently concluded DAC 2021. The talk was given by Michael Jackson, Ph.D. Corporate VP, Research and Development at Cadence. The semiconductor market couldn’t have developed to even a fraction of its size today without the electronic design automation (EDA) industry. Michael takes us through his view of how EDA enabled Moore’s Law and the changes happening to EDA as driven by AI/ML. The last part of his presentation covers the integration changes needed to drive the continued growth of the semiconductor industry. The following is a synthesis of what I garnered from his talk titled “More Than Moore and Charting the Path Beyond 3nm.” You can listen to Michael’s entire talk from the TechTalks track of DAC 2021 virtual sessions.

Three ways EDA has fundamentally enabled Moore’s Law

Process technology advances is an obvious enabler of Moore’s Law as it is intrinsic to it. Another, not so intrinsic, nonetheless a fundamental enabler of Moore’s Law is EDA. The three ways EDA has enabled Moore’s Law are design methodology, EDA tool turnaround time (TAT) and process technology enablement.

Design Methodology

EDA has advanced from polygon pushing to transistor-level to cell-based to IP re-use design methodology development and support. At every step of this progress, EDA has delivered an average 10x productivity boost.

EDA Tool TAT

If tool run time could be reduced in half (say from 8 hours to 4 hours), that translates to a huge benefit for a designer. Since the early 2000s, EDA industry began focusing more on such core values and less on features for features sake. Inspired by Moore’s Law, tool TAT improvement became a major focus for each release of tools within the EDA industry.

Michael shares examples of systematic runtime performance improvements release over release. Synthesis products runtime improvements of 1.5x with every release as measured statistically over suite runs versus over just a few select designs. Emulation capacity increase of more than 10,000-fold over the last 30 years. Spectre® X simulator’s 10x speed improvement over Spectre APS while maintaining Spectre golden accuracy standards.

Process Technology Enablement

Process technology advances impact EDA tools with hard and soft requirements that must be addressed. Hard requirements are changes to each process technology node that must be handled by EDA tools. Examples of hard requirements are changes such as double-patterning, special Via support, DRC rule enablement and extraction enablement. Place and Route tool is very highly dependent on process technology driven hard requirements. At the other end of the spectrum are RTL simulation tools with very low dependency on process technology. And then there are soft requirements such as accuracy improvements to enable improved analysis and optimizations at each process node. Low-voltage accuracy and aging analysis are examples of soft requirements that are process node dependent.

ML-enabled EDA is the next Big Thing

EDA is full of NP hard/NP complete problems that are non-trivial to solve and require exponential run times. Because of this, overdesign and margin inefficiencies are traditionally built into designs to save on run times. Machine learning’s robust, rapid pattern-matching framework can reduce overdesign and margin inefficiencies.

ML-Based EDA can

• help change design methodology as well as help improve run times of EDA tools
• improve PPA results

Cadence’s ML-enabled EDA tools and capabilities span a wide spectrum of functional areas. Refer to Figure below.

Cadence Cerebrus™ digital implementation full flow, for example, delivers PPA and runtime improvements and frees engineering resources to work on more designs. This has been covered in detail in an earlier post. Michael provides a number of examples of improvements achieved through ML-enabled EDA.

Solution requirements needed to support the More than Moore Era

The slowdown of Moore’s Law has accelerated the growth of complex system designs leading to heterogeneous system integration. This era is termed as the More than Moore era. Just as Moore’s Law era was enabled by EDA, so will the More than Moore era in the form of 3D design methodology, 3D EDA tool TAT improvements, and 3D process technology enablement. Today’s complex systems call for integrating digital, analog, RF, sensors, passives and fluidics in 3D ICs, and on PCBs.

Cadence has been investing in multi-chip(let) packaging for a long time. When dealing with 3D-IC requirements, already complex and time-consuming tasks may take an even larger scale. For example, let’s consider static time analysis (STA) and the number of corners for a signoff. When going from a single die implementation to a chiplet implementation, the number of corners for signoff could increase 10x-100x depending on the design. Cadence’s Rapid, Automated Inter-Die (RAID) analysis significantly reduces STA corner data and TAT. Cadence has also developed and incorporated other capabilities into Tempus for enhancing efficiencies for 3D-ICs. In order to be able to avoid costly overdesign of individual dies and packages that make up a 3D-IC, a fully integrated platform is needed. A platform that integrates die implementation, package design, power, thermal and timing analysis and DRC/LVS check, all operating on an multi-technology common database.

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