WP_Term Object
(
    [term_id] => 15
    [name] => Cadence
    [slug] => cadence
    [term_group] => 0
    [term_taxonomy_id] => 15
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 420
    [filter] => raw
    [cat_ID] => 15
    [category_count] => 420
    [category_description] => 
    [cat_name] => Cadence
    [category_nicename] => cadence
    [category_parent] => 157
    [is_post] => 1
)

Complete IP port-folio built in less than two years!

Complete IP port-folio built in less than two years!
by Eric Esteve on 12-18-2013 at 10:47 am

We have posted several blogs related to Cadence IP strategy, or I should say new strategy. Each of these blogs was dealing with a particular product, like PCI Express gen-3 Controller IP, latest DDR4 Memory Controller or Wide I/O. This approach was equivalent to describe trees, one after one, and finally ignoring the forest! It’s possible to define a date, the T0 when Cadence has decided to consider implementing this new strategy to develop IP business: at the end of Q1 2012, when martin Lund came on board as Senior VP, IP Group. Since then, in about 20 months, Cadence has made numerous acquisitions: Cosmic Circuits, Evatronix, the SerDes Design Team of PMC Sierra and Tensilica, the latest being the most expansive and also the most ambitious. Engaging in the DSP/CPU IP core business is certainly a strong signal to the market that Cadence takes IP seriously! As far as I am concerned, I think that Cadence positioning in the Interface IP market is also a strong signal, and could be even more rewarding in term of volume of business on the mid-term, or within three to five years.

I was trying to better understand Cadence strategy for MIPI IP, as since Cosmic Circuit acquisition bringing MIPI PHY to the company at the beginning of 2013, MIPI IP port-folio has been drastically enlarged as you can see on the above picture. On top of the main and well-known interfaces like DSI, CSI-2, CSI-3, DigRF or LLI, Cadence has also developed UniPro, SLIMBus (Manager and Device), Battery Interface (BIF) and Soundwire. This sounds like a strong investment and illustrate a clear positioning: potential customer can find any of the MIPI interface he may need. If we look at emerging Interfaces like Mobile Express (M-PCIe), SuperSpeed IC (SSIC) or Universal Flash Storage (UFS), Cadence didn’t give it a miss and I guess that the R&D team should be busy developing these numerous IP.

Addressing the customer concern to consider Silicon proven IP solution rather than slides (extremely relevant care-about!), Cadence has integrated several of these MIPI IP into demonstration board, including M-PHY and D-PHY Test Chip. This is a good way to position MIPI IP as a potential winning solution: wide offer, Silicon proven PHY and Controller is clearly attractive.

As I have mentioned a complete IP port-folio, the above picture is the right illustration of Cadence ambition to propose as many IP solutions as possible, addressing various and different market segments: Mobile, Storage, Networking, PC and Peripherals and Consumer Electronics. Why investing so much? Because most of these IP represent a large and fast growing market! IPNEST has built the forecast for Interface IP (column 1, 3, 4, 5 and 6) up to 2017, the market associated will grow with a 12% CAGR during the next five years, reaching ¾ $Billion by 2017, see picture below:

Just a word from Martin Lund, from the still up to date September newsletter: “Cadence combined our expertise in interface IP, analog/mixed signal technologies, and system verification to offer customers a complete and full-featured NVM Express interface subsystem,” said Martin Lund, senior vice president, Research and Development, SoC Realization Group, Cadence. “Without this subsystem approach, SoC designers would need to source their interface component IP separately and drive integration on their own, often increasing their design risk and overall development time for new SoCs.”

Eric Esteve from IPNEST

More Articles by Eric Esteve …..

lang: en_US