With growing SoC size, complexity, software and hardware content in it and shrinking time-to-market, the SoC design completion in time has become increasingly dependent on IP which need to be sourced (internally or externally), customized according to the design need and integrated together into the SoC. While IP providers… Read More
At the beginning of December in Paris I had the opportunity to make a presentation to a very impressive audience, technical gurus from companies contributing to MIPI Alliance specification were here, including ST-Microelectronics, Intel, Qualcomm, TI, Toshiba, Nokia, Samsung, to name a few. … Read More
We have posted several blogs related to Cadence IP strategy, or I should say new strategy. Each of these blogs was dealing with a particular product, like PCI Express gen-3 Controller IP, latest DDR4 Memory Controller or Wide I/O. This approach was equivalent to describe trees, one after one, and finally ignoring the forest! It’s… Read More
We have recently commented the announcement from MIPI Alliance and PCI-SIG, allowing PCI Express to be used in martphone, Media tablet and Ultrabook, while keeping decent power consumption, compatible with these mobile devices. The secret sauce is in the High Speed SerDes function selected to interface with these high data … Read More
MIPI set of specifications (supported by dedicated controllers) are completed by a PHY function, the D-PHY or the M-PHY function. The D-PHY was the first to be released, and most of the MIPI functions supported in a smartphone we are using today probably still use a D-PHY, but the latest MIPI specifications have been developed based… Read More
If you are not familiar with SuperSpeed USB standard (USB 3.0), you may understand this press release from Rahman Ismail, chief technology officer of the USB Implementers Forum, as simply claiming that USB 3.0 will be used in smartphone & media tablet this year… but, if you are familiar with the new standard, you are just confused!… Read More
