WP_Term Object
(
    [term_id] => 15
    [name] => Cadence
    [slug] => cadence
    [term_group] => 0
    [term_taxonomy_id] => 15
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 595
    [filter] => raw
    [cat_ID] => 15
    [category_count] => 595
    [category_description] => 
    [cat_name] => Cadence
    [category_nicename] => cadence
    [category_parent] => 157
)
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WP_Term Object
(
    [term_id] => 15
    [name] => Cadence
    [slug] => cadence
    [term_group] => 0
    [term_taxonomy_id] => 15
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 595
    [filter] => raw
    [cat_ID] => 15
    [category_count] => 595
    [category_description] => 
    [cat_name] => Cadence
    [category_nicename] => cadence
    [category_parent] => 157
)
Cadence
Posted on by Daniel Payne

Two New TSMC-Cadence Webinars for Advanced Node Design

Two New TSMC-Cadence Webinars for Advanced Node Design
by Daniel Payne on 04-15-2013 at 3:43 pm
Categories: Cadence, EDA, Foundries, TSMC

Foundries and EDA vendors are cooperating at increasing levels of technical intimacy as we head to the 20nm and lower nodes. Cadence has a strong position in the EDA tools used for IC design and layout of custom and AMS (Analog Mixed-Signal) designs. They have created a series of webinars to highlight the design challenges and new approaches required. In 10 days you can learn about addressing Layout-Dependent Effects (LDE) as part II. See my blog on the part I webinar.

Interested in advanced node designs? Enhance your expertise with two new webinars from TSMC and Cadence.



Addressing Layout-Dependent Effects
At 9am and 6:30pm PDT on April 25, Manoj Chacko and Bala Kasthuri of Cadence and Jason Chen from TSMC will present, “Variation-Aware Design: Detecting and Fixing Layout-Dependent Effects Using the Cadence® Virtuoso® Platform, Part II, a sequel to Variation-Aware Design, Part I. You’ll learn about:

  • The solutions jointly developed by Cadence and TSMC, to provide a complete layout-dependent effect (LDE) flow for circuit and layout designers working at 28nm and below
  • When, why, and how you should incorporate TSMC’s LDE-API with Cadence Virtuoso tools into an analog, custom, or mixed-signal design flow to achieve the most efficient design cycle time

Managing Design Complexity at 20nm
At 9am and 6:30pm PDT on May 23, Rahul Deokar and John Stabenow of Cadence and Jason Chen from TSMC will present, “20nm Design Methodology: A Completely Validated Solution for Designing to the TSMC 20nm Process Using Cadence Encounter®, Virtuoso, and Signoff tools.” You’ll learn about:

  • The TSMC-Cadence solutions in the TSMC 20nm Reference Flow, tools certification, and Cadence tools and methodology to enable 20nm design with double patterning technology (DPT)-aware capabilities, to reduce design complexities and deliver required accuracy
  • How in-design DPT and design rule checking (DRC) can improve your productivity
  • How both colored and colorless methodologies are supported, and data is efficiently managed in front-to-back design flows
  • How local interconnect layers, SAMEMASK rules, and automated odd-cycle loop prevention are supported
  • How mask-shift modeling with multi-value SPEF is supported for extraction, power, and timing signoff

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