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IBM Tapes Out 14nm ARM Processor on Cadence Flow

IBM Tapes Out 14nm ARM Processor on Cadence Flow
by Paul McLellan on 10-30-2012 at 7:33 pm

 An announcement at the ARM conference was of a joint project to tape out an ARM Cortex-M0 in IBM’s 14nm FinFET process. In fact they taped out 3 different versions of the chip using different routing architectures to see the impact on yield.

This was the first 14nm ARM tapeout, it seems. I’m sure Intel has built plenty of 14nm test chips but it seems safe to assume none of them included ARM processors.

Cadence went into a lot of detail about how the flows need to be changed, especially to cope with double patterning and to do transistor extraction of the FinFETs themselves.

For me the most interesting part was that IBM actually revealed a certain amount about their process. The FinFETs need to manufactured in a complete grid and then cut to separate them into individual transistors, some of which might not actually be used. The photograph above shows the FinFETs in yellow running horizontally with the vertical metal to interconnect them into standard cells (I would have a decent picture except that the meeting had the oddly inconsistent policy that we couldn’t have a copy of the presentation but we could take pictures of the screen).

Here are some more details of the process[TABLE] align=”left” style=”width: 470px”
|-
|
| style=”text-align: center” | 32nm
| style=”text-align: center” | 28nm
| style=”text-align: center” | 20nm
| style=”text-align: center” | 14nm
|-
| Architecture
| Planar
| Planar
| Planar
| FinFET
|-
| Contacted poly pitch
| 126nm
| 114nm
| 90nm
| 80nm
|-
| Metal pitch
| 100nm
| 90nm
| 64nm
| 64nm
|-
| Local interconnect
| No
| No
| Yes
| Yes
|-
| Self-aligned contact
| No
| No
| No
| No
|-
| Strain engineering
| Yes
| Yes
| Yes
| Yes
|-
| Double patterning
| No
| No
| Yes
| Yes
|-

es at IBM:

Just like the Global Foundries 14nm announcement, this has a metal pitch unchanged from 20nm. Some cells might be smaller but in general I think this means that designs won’t really be any smaller using this technology. Lower power, faster, better leakage. But not smaller.

In the TSMC keynote earlier, the focus was on PPA (power, performance, area). We used to say power, performance, price. But the big question is how costly these processes will be compared to 28nm which looks set to be a workhorse process for a long time. The IBM/Cadence presentation was the same. Of course it is early in development and no yield optimization has been done but somehow the fact that nobody is bragging about how cheap the technology is and how everyone will want to use it immediately implies that it will not be cheaper. And worse, that designs will not get hundreds of times cheaper after several process generations.

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