Cadence at Semicon West Next Week: 2.5D and 3D

Next week it is Semicon West in the Moscone Center from Tuesday to Thursday, July 10-12th. Cadence will be on a panel session during a session entitled The 2.5D and 3D packaging landscape for 2015 and beyond. This starts with 3 short keynotes:

• 1.10pm to 1.25pm: Dr John Xie of Altera on Interposer integration through chip on wafer on substrate (CoWoS) process.
• 1.25pm to 1.40pm: Ryusuku Otah of Fujitsu on Large SIP for computer and networking application with 2.5D, 3D structure.
• 1.40pm to 1.55pm: Dr Huili Fu of HiSilicon Technologies on The demands and the challenges of TSV technology application in IC and system.

Then from 2.20pm to 3.30pm there is a panel session on Ecosystem and R&D collaboration. Cadence will be represented by Samta Bansal, who I talked to about Cadence’s joint work with TSMC that they announced at DAC.

As I’ve said before, I think that 2.5D (and eventually 3D) are going to be very important since it is not clear that we will be able to continue to keep on track with lithographic scaling. With double and triple patterning we can manufacture but it is very expensive and wafer prices are going up fast. EUV still looks a long way from possible commercialization and it may never get there. In the meantime, high levels of integration can be achieved with CoWoS along with the advantage of being able to mix die from different processes. We are at the early stages of this and there is still lots of work to be done, both on the EDA side but more so on the ecosystem and supply chain (who does what? when do you test? how do you ship ultra-thin silicon around without breaking it? etc). Since this is the topic of the panel session, it should be interesting to hear.

The session is free to attend if you are registered for Semicon.