At DesignCon 2020, ANSYS sponsored a series of very high-quality presentations. Some focused on advanced methods and new technology exploration and some provided head-on, practical and actionable capabilities to improve advanced designs. The presentation I will discuss here falls into the latter category. The topic was presented by Anand Raman, senior director of application engineering for on-chip EM solutions at ANSYS. Anand is one of those people who has infectious enthusiasm. He will draw you into whatever topic he is presenting and get you involved. Given the impact of his material, it was quite easy to do in this case.
Anand began by pointing out that most people understand the need for electromagnetic (EM) analysis for high-frequency RF designs (chip and board). The structures and operating frequencies of this class of design utilize “purposeful inductance” that needs to be modeled. He then pointed out that these challenges can also exist in ultra-high-speed digital designs, in subtle and hard-to-find ways that can cause large problems due to parasitic inductance. A collection of correctly designed and verified blocks can fail when assembled onto a chip due to remote coupling effects. Power/ground networks can become channels to create these subtle problems.
Anand pointed out that extremely thin routes that run long distances and carry very high-speed data is a formula for extreme inductance effects. Capacitance extraction has been widely used in digital design for a while now. It’s time to consider inductance effects as well. Parasitic inductance causes two problems – signal distortion and parasitic coupling due to the magnetic field.
It turns out that an EM-aware design flow can do more than ensure a working chip. It can also provide the opportunity to improve circuit density as well. The figure below summarizes some of these effects for two generations of the same design. The second one is over 37% smaller, owing to the ongoing and complete modeling of all EM effects, allowing for a more aggressive design.
Going back to the subtle and non-intuitive nature of magnetic coupling, Anand provided a good graphic to explain the problem, see below. The third loop mentioned below could be created by the thousands of structures in a power distribution network.
ANSYS provides a platform of tools to get to the required level of coverage for a true EM-aware design flow. These tools integrate with existing digital design flows and provide several levels of analysis support. The tools, and their field of application, are summarized below.
Regarding the other benefits of an EM-aware design flow, several examples were presented based on real designs. In one case, shown below, active circuitry was folded under an inductor, resulting in substantial area savings. This was made possible by analysis from the previously mentioned ANSYS EM tool platform to ensure this change did not introduce EM coupling effects. VeloceRF was also used to synthesize a much smaller inductor. Overall, there was a 66% area saving with slightly better performance.
Several other real design examples were presented that highlight the way subtle EM coupling can cause significant design problems. These examples included a working chip that degraded in the package due to EM crosstalk from the ground net to the first few package layers. Other cases of degradation due to coupling through the package were presented. Another interesting case illustrated how the seal ring in a chip cause an inductive coupling loop.
I would say Anand made a strong and passionate case for the benefits of an EM-aware design flow. To check out an example of a customer case study on the topic of de-risking high-speed serial links from on-chip electromagnetic crosstalk and power distribution issues, click HERE.