Aldec Adds Simulation Acceleration for Microchip FPGAs

Despite the fact that FPGA based systems make it easy to add ‘hardware in the loop’ for verification, the benefits of HDL and gate level simulation are critical for finding and eliminating issues and bugs. The problem is that software simulators can require enormous amounts of time to run full simulations over sufficient time intervals to locate and eliminate problems. This is where HDL simulation acceleration can help close the gap and improve productivity. Aldec has a white paper titled “HDL Simulation Acceleration Solution for Microchip FPGA Designs” that discusses the topic in detail and provides insight into how designers can gain the benefits of speedup from hybrid software and hardware based simulation acceleration to rapidly identify and resolve issues.

FPGA based systems are heavily used in aerospace, aviation, and automotive markets. Some of these markets have very specific requirements for reliability and radiation tolerance (RT). FPGAs, such as those from Microchip offer excellent solutions for these markets. Microchip’s PolarFire FPGA offers RT and their SmartFusion2 comes with an embedded ARM Cortex-M3.

The Aldec paper covers each of the verification processes that must be addressed. There is RTL simulation with all the necessary test benches. Then comes post-synthesis simulation, which comes with much more simulation overhead. This is also when any potential discrepancies between gate level and RTL results are examined. Also, IP cores which should be independently verified need to be simulated in-system to ensure proper integration. As always there are regression tests that must be performed throughout the project lifetime. On top of this there is the use of constrained random testing to catch difficult to find corner cases. Constrained random testing usually needs massive amounts of simulation. Lastly, any debugging requires problem identification, fix implementation and verification which calls for the features found in HDL simulation.

In the white paper Aldec describes their solution for hardware acceleration of simulation of FPGA based system – HES-DVM. It offers simulation acceleration, emulation and physical prototyping. In the case of special purpose applications like RT or where there is vendor specific IP, they offer the ability to use the target FPGA for simulation. This means that IP can run natively using specialized features of the FPGA during simulation. The test benches and any HDL needed for debugging run on the Aldec Riviera-PRO or Active-HDL HDL simulators which are tightly integrated or with other simulators using PLI or VHPI interfaces. This approach requires no changes to testbenches because the DUT-wrapper handles the connection between the HDL simulator and the simulation running on the HES board.

According to Aldec, the key features of their hybrid simulation solution are as follows. First off there is automated design setup with their Design Verification Manager (DVM). Next is HDL compilation of VHDL, Verilog or SystemVerilog to elaborate the design. Even mixed HDL designs are supported. Incremental synthesis follows converting the HDL into high level net lists. This approach to synthesis means that individual blocks can be resynthesized without any need to resynthesize the full design. The granularity can be controlled by creating synthesis groups to optimize results. Aldec’s DVM gives users control over debug probes so that they are available after synthesis of HDL. DVM also supports FPGA technology primitives that are instantiated in the HDL/RTL code. The same is true for hard macros of third-party IP cores. Aldec DVM provides an interface to map memory modules into on-chip or on-board memories. Through this it is possible to offer back-door interfaces to read or write memory during runtime. This greatly improves debugging capabilities. DVM lets users specify which signals are of interest, so they are preserved. Also, specific blocks can be flagged so that they run in the simulator and not in the FPGA.

The white paper concludes with an example of a scenario for verifying a radar design. Aldec has a unique and powerful solution for avoiding the bottlenecks and delays of full system HDL simulation. At the same time, it offers the visibility and debugging power found in HDL based simulation. On top of this they have added target FPGA based simulation, so that vendor specific IP is fully supported. The Aldec simulation acceleration solution offers the performance and flexibility needed to sign off complex aerospace, aviation, military and automotive systems. If you are interested the full white paper is available on the Aldec website.