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10 to 100X faster HDL Simulation Speeds

10 to 100X faster HDL Simulation Speeds
by Daniel Payne on 04-24-2013 at 10:44 am

Speed, capacity, accuracy – these are the three major EDA tool metrics that we pay attention to and that enable us to design and verify an SoC. Talk to any design or verification engineer and ask if they are satisfied with the time that it takes to simulate their latest design, or to verify that it meets spec and is functionally correct. That answer that you hear is, “No, I’m not satisfied, simulation of my RTL takes way too long.”

The EDA industry has responded to this challenge with several verification approaches:

  • HDL simulators – powerful debugging capabilities, good signal visibility, moderate cost, too slow
  • Emulators – faster speeds than HDL simulation, pricey, lack of signal visibility
  • FPGA Prototyping – faster speeds then HDL simulation, moderate cost, unconnected with HDL simulator

In 2011 the engineers at Aldec came up with an approach that combines an HDL simulator with an FPGA-based prototyping board, dubbed the HES XCELL. So a design or verification engineer can now use a familiar HDL simulator with debugging features, connected to an FPGA prototyping board to get a 10X to 100X speed up over just using an HDL simulator.

With this accelerated simulation approach the engineer continues to use a familiar HDL simulator to control the simulation and see results in the waveform viewer, while the actual design is simulating on the FPGA hardware to provide the speed up. You still determine what simulates in the HDL simulator versus the prototype board, so a design engineer can place new blocks in the HDL simulator and re-used blocks in hardware. As your design work is completed, you would place only your testbench in the HDL simulator, while the Design Under Test (DUT) is placed in the hardware:

8051 Example
The popular 8051 core and testbench were simulated in Aldec’s HDL simulator, called Riviera-PRO:

The 8051 core was using 97.08% of the CPU, while the testbench was using only 1.29% of the CPU. If we placed the 8051 core in hardware, instead of running in the HDL simulator, then a significant time speed-up can be had. Here’s a chart of the speed-up factor that you can expect with this accelerated simulation approach:

Getting Your Design Into Hardware
There are five steps to get your RTL design into hardware for the accelerated simulation:

[LIST=1]

  • Import your compiled HDL using the Design Verification Manager
  • Configure your design for debugging
  • Use logic synthesis on the blocks that will be accelerated into hardware
  • Partition your design between HDL-based simulation and accelerated simulation
  • Place and route your design for use in the FPGA

    Aldec uses an FPGA prototyping board with Xilinix Virtex 5 parts, you can also use boards from the DINI Group or Synopsys HAPS.

    Summary
    The approach of accelerated simulation has been shown to speed up HDL simulation results by a factor of 10X to 100X, allowing you to complete your verification quicker, while providing full debugging like in a traditional software-based HDL simulator.

    Further Reading

    White Paper: Simulation Acceleration with HES XCELL

    *lang: en_US


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