What I Learned About FPGA-based Prototyping

Today I attended an Aldec webinar about ASIC and SoC prototyping using the new HES-7 Board. This prototyping board is based on the latest Virtex-7 FPGA chips from Xilinx.

You can view the recorded webinar here, which takes about 30 minutes (should be available in a few days). I first blogged about the HES-7 two months ago, ASIC Prototyping with 4M to 96M Gates.
Should I build my own FGPA prototype board?

• Risk
• Budget
• PCB expertise
• Can the platform handle growth
• Most flexibility

Buy a FPGA platform off the shelf?

• It’s proven to work
• SW/HW verification possible
• Daughter boards add flexibility
• More time to focus on ASIC design

Current Prototyping Challenges

• Does my RTL fit onto the board?
• Do I have to partition my design across FPGAs?
• Are there enough I/O between FPGAs?
• Does signal skew affect my timing?
• Can I debug what’s happening on the board or in the FPGA, is there enough memory?

Using the Xilinix Virtex-7 FPGA devices for prototyping

• About 2M logic cells for your ASIC design
• 50% less power than previous FPGA families
• Up to 21Mbits of RAM and 2,160 DSP Slices
• Stacked Silicon Interconnect (SSI) – uses four FPGA die combined onto a silicon interposer
• Much less partitioning, even a single FPGA

Xilinx Virtex-7 Device

Features of the Aldec HES-7

• 4M, 8M, 12M, 24M, 96M gate configurations
• One or two FPGAs used per board
• Daughterboard connector for expansion
• Lower ASIC prototyping costs
• 720 single-ended and 360 differential-ended connections
• 44 gigabit transceiver lines
• 5 global clock inputs
• 322 high-speed inter-FPGA connections
• Backplane up to 35 Gbps
• 60 differential global clock input pins
• Up to 16GB of DDR3 memory (64GB with 4 HES boards)
• Micros SD card socket
• PCI-Express, USB 2.0/3.0, JTAG, 2 SATA, self-diagnostics
• Ethernet, WiFi, Bluetooh, HDML, Audio codec
• Connectors: ARM, RS232, I2c, SPI, GPIO
• Expandable: 1, 2, 4 boards
• User for acceleration or emulation or virtual modeling

HES-7 with a single FPGA

HES-7 with dual FPGAs, includes Zynq

Questions:

Q: How do you configure the FPGAs on the board?
A: Using two JTAG chains with standard cables.

Q: Is there support for emulation?
A: Support for HES-7 emulation in Q1 2013.

Q: Do you provide bitstream generation software?
A: No, that’s provided by Vivado from Xilinx.

Q: Max data transfer?
A: 16 x 6.6Gbps = 105Gbps for FPGA1 GTX BP interface 28 x 6.6Gbps = 184.8Gbps for FPGA1 GTX BP interface
60 LVDS links x 1.2Gbps= 72Gbps for FPGA1 LVDS BP interface
120 LVDS links x 1.2Gbps= 144Gbps for FPGA2 LVDS BP interface

Current configuration of Virtex7 chips on HES-7 board is able to run up to 505.8Gbps = 105Gpbs + 184.8Gbps + 72Gbps + 144Gbps using all high speed connections on BP connector.

Q: Max data transfer between FPGAs?
A: Up to 201.6 Gbps.

Summary
This is another fast-paced webinar that introduces how Aldec has built and delivered a family of FPGA prototyping boards that span from 2M gates up to 96M gates. What sets the Aldec approach apart from others is how open the backplane spec is, which would allow you to integrate any other hardware using a daughterboard. Pricing looks attractive, so I’m looking forward to talking with the first users of this prototyping board to learn how usable it is for their projects.