Banner Electrical Verification The invisible bottleneck in IC design updated 1
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Two Fun Things To Do at SEMICON West on July 9, 2019

Two Fun Things To Do at SEMICON West on July 9, 2019
by Randy Smith on 07-01-2019 at 10:00 am

 

I will be at SEMICON / EE Design West on Tuesday, July 9, 2019, and so should you!

Quantum computing will be a hot topic at SEMICON West and on Tuesday, July 9, the IBM Quantum Computer will be on display at the Smart Design Pavilion in the South Hall (Moscone Center) from 10:00am to 5:00pm. It looks like no other computer I have ever… Read More


Double-digit semiconductor decline in 2019

Double-digit semiconductor decline in 2019
by Bill Jewell on 06-27-2019 at 4:00 pm

The global semiconductor market is headed for a double-digit decline for the year 2019 after a decline of 15.6% in first quarter 2019 from fourth quarter 2018. According to WSTS (World Semiconductor Trade Statistics) data, this was the largest quarter-to-quarter decline since a 16.3% decline in first quarter 2009, ten years … Read More


SPIE Advanced Lithography Conference – Imec design papers

SPIE Advanced Lithography Conference – Imec design papers
by Scotten Jones on 06-27-2019 at 10:00 am

At the SPIE Advanced Lithography Conference Imec presented several design papers and I have had the opportunity to review the papers and speak with the authors. In this summary I am going to address three emerging areas in order of when I think they may be implemented from soonest to latest.

Specifically, I will discuss:

  1. Buried Power
Read More

Micron beats subdued guidance on output cuts

Micron beats subdued guidance on output cuts
by Robert Maire on 06-26-2019 at 5:00 am

2020 capex likely down at least 20% vs 2019 DRAM & NAND price drops versus slowing capacity. Investors happy cause it could have been worse.

Micron reported $1.05 in Non-GAAP EPS beating street consensus of $0.79 by $0.26. While this looks like a big beat, we would remind investors that estimates for the quarter were about… Read More


Lithography For Advanced Packaging Equipment

Lithography For Advanced Packaging Equipment
by Robert Castellano on 06-24-2019 at 10:00 am

Advanced IC packaging, such as fan-out WLP (Wafer Level Packaging) and 2.5D TSV (Through Silicon Via) will drive the packaging equipment market, particularly lithography. This will help specific equipment manufacturers in 2019, since the WFE (Wafer Front End) market will drop 17%. But the Back-End lithography market, led … Read More


Meet the Experts @ ES Design West!

Meet the Experts @ ES Design West!
by Daniel Nenni on 06-18-2019 at 10:00 am

SEMICON West and ES Design West are right around the corner here in San Francisco and I wanted to point out the Meet the Experts segment in the appropriately named Meet the Experts Theater. Great idea really and a super great line-up. The best part of course is actually meeting the experts. Over my 35 year semiconductor career I have… Read More


#56thDAC SerDes, Analog and RISC-V sessions

#56thDAC SerDes, Analog and RISC-V sessions
by Eric Esteve on 06-14-2019 at 5:00 am

The good news is that the next five DAC events will take place in Moscone Center in San Francisco! If going to Las Vegas from the Bay area is an easy trip, coming from Europe to Las Vegas makes it a 24+hours journey… One obvious consequence was the poor attendance to the exhibition floor. But let’s be positive and notice that the number… Read More


In Their Own Words: eSilicon Corporation

In Their Own Words: eSilicon Corporation
by Daniel Nenni on 06-01-2019 at 8:00 am

eSilicon was one of the first companies to focus on making the benefits of the fabless semiconductor movement available to a broader range of customers and markets. The company is credited with the creation of the fabless ASIC model. In this section, eSilicon shares some of its history and provides its view of the ever-changing Read More


Opening a new front in multi faceted trade war

Opening a new front in multi faceted trade war
by Robert Maire on 05-30-2019 at 5:00 am

We had warned in our May 10th note about the rare earth element risk.  It is one of the few remaining leverage points that China has left that has a potentially strong impact on the US much similar to the US’s impact on Huawei and perhaps even worse. Cutting the US off from rare earth elements is clearly worse than cutting Huawei
Read More

Selecting an ASIC Package

Selecting an ASIC Package
by Daniel Nenni on 05-29-2019 at 10:00 am

Semiconductor chip package technologies have evolved throughout the years to the point where hundreds of package types are available today. 

Most applications will require the more general, single-element packaging for integrated circuits and the other components such as resistors, capacitators, antenna etc. However,… Read More