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Prototyping

FPGA based Prototyping

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Time-saving modules expand Prototype Ready family

Time-saving modules expand Prototype Ready family
by Don Dingee on 07-13-2016 at 4:00 pm
Categories: FPGA, S2C EDA

A big advantage of FPGA-based prototyping is the ability to run real-world I/O at-speed, significantly faster and more accurately than hardware emulation systems typically requiring a protocol adapter. Dealing with real-world I/O means more thorough verification of SoC integration, and the opportunity to optimize systems… Read More

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S2C tutorial and PROTOTYPICAL debut at DAC

S2C tutorial and PROTOTYPICAL debut at DAC
by Don Dingee on 05-18-2016 at 4:00 pm
Categories: Automotive, FPGA, IoT, S2C EDA

It’s been a busy few days here in Canyon Lake, and we’re ready to share exciting news in advance of #53DAC coming up on Monday, June 6[SUP]th[/SUP]. S2C is offering a technical program tutorial on “Overcoming the Challenges of FPGA Prototyping” followed by the launch of our latest book project, “PROTOTYPICAL”, including a field… Read More

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Software-Driven Verification Drives Tight Links between Emulation and Prototyping

Software-Driven Verification Drives Tight Links between Emulation and Prototyping
by Bernard Murphy on 04-28-2016 at 12:00 pm
Categories: Cadence, EDA, Prototyping

I’ve mentioned many times what has become a very common theme in SoC and system verification – it has to be driven by the software because any concept of exhaustively verifying “everything” is neither feasible nor meaningful. Emulation has become a critical component of this flow in validating and regressing… Read More

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Solving the Next Big SoC Challenges with FPGA Prototyping

Solving the Next Big SoC Challenges with FPGA Prototyping
by Daniel Nenni on 03-01-2016 at 4:00 pm
Categories: EDA, FPGA, S2C EDA

The health of the semiconductor industry revolves around the “start”. Chip design starts translate to wafer starts, and both support customer design wins and product shipments. Roadmaps develop for expanding product offerings, and capital expenditures flow in to add capacity enabling more chip designs and wafer starts. If… Read More

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Aldec reprograms HES7 for AXI4 speed

Aldec reprograms HES7 for AXI4 speed
by Don Dingee on 02-26-2016 at 4:00 pm
Categories: Aldec, EDA, FPGA, Prototyping

FPGA-based prototyping firms are all grappling with the problem of higher speed connectivity between a development host and their hardware. Aldec is announcing their solution at DVCon 2016, turning to an AMBA AXI4 interface bridged into a host with PCIe x8.

Faster host interfaces deliver dual benefits in FPGA-based prototyping.… Read More

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S2C opens up FPGA prototyping for PCIe fabrics

S2C opens up FPGA prototyping for PCIe fabrics
by Don Dingee on 02-23-2016 at 4:00 pm
Categories: EDA, FPGA, S2C EDA

Reconfigurable computing began with FPGA cards dropped into expansion slots in workstations. FPGA-based prototyping vendors tended away from that model as interconnect speeds rose and cabling complexity between modules increased. Much faster PCIe interfacing and bigger FPGAs mean revisiting the concept.… Read More

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Fastest SoC time-to-success: emulators, or FPGA-based prototypes?

Fastest SoC time-to-success: emulators, or FPGA-based prototypes?
by Don Dingee on 02-11-2016 at 12:00 pm
Categories: EDA, FPGA, S2C EDA

Hardware emulators and FPGA-based prototyping systems are descendants of the same ancestor. The Quickturn Systems Rapid Prototype Machine (RPM) introduced in May 1988 brought an array of Xilinx XC3090 FPGAs to emulate designs with hundreds of thousands of gates. From there, hardware emulators and FPGA-based prototyping … Read More

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Should there be a 5-second IoT chip rule?

Should there be a 5-second IoT chip rule?
by Don Dingee on 01-12-2016 at 12:00 pm
Categories: FPGA, IoT, S2C EDA

Kids have a tendency to put things in their mouths. Any parent can relate to the statement, “Put that down! You don’t know where it’s been!” After the first child, concern usually relaxes quite a bit. People joke about a 5-second rule on the premise if an object was just dropped on the floor, it may not be contaminated yet.… Read More

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Breaking the Limits of SoC Prototyping

Breaking the Limits of SoC Prototyping
by Pawan Fangaria on 11-17-2015 at 12:00 pm
Categories: EDA, FPGA, S2C EDA

Earlier this month during my conversation with Dr. Walden C. Rhines, he emphasised the need for our next generation designers to think at system level and design everything keeping the system’s view in mind. The verification will go through major transformation at the system level. I can see the FPGA prototyping systems already… Read More

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A (R)evolution in Hardware-based Simulation Acceleration

A (R)evolution in Hardware-based Simulation Acceleration
by Tom Dillinger on 11-16-2015 at 9:45 am
Categories: Cadence, EDA, Prototyping

The most exciting products in our industry are those that are both evolutionary and revolutionary. Cadence has just announced an update to their hardware simulation acceleration platform – Palladium Z1 – which continues the evolution of the unique capabilities of processor-based acceleration, plus a revolutionary approach… Read More